近年來，非晶相銦鎵鋅氧化物薄膜電晶體由於其相較於低溫多晶矽薄膜電晶體在大尺寸基板有較好的一致性、較低的製造成本及較小的漏電流等優點而受到相當大的注目，且相較於非晶矽薄膜電晶體也有更高的載子移動率、較高的穩定性及對可見光較高的穿透度。然而非晶相銦鎵鋅氧化物薄膜電晶體在偏壓的情況下造成臨界電壓漂移進而影響電路使用壽命，因此必須在設計閘極驅動電路及畫素電路時被考慮。
針對上述之問題，本論文提出了三個新式使用非晶相銦鎵鋅氧化物薄膜電晶體設計的電路，並經由模擬軟體證明所提出電路之可行性。第一個電路為適用於高解析度及窄邊框液晶顯示器之閘極驅動電路，由四顆薄膜電晶體與兩顆電容所組成，特色為利用三組重疊的時脈訊號抑制電晶體臨界電壓之變異性，且輸入及驅動薄膜電晶體都可用來作為充電及放電路徑進而減少電路中的元件數，並藉由時脈訊號的重疊區間操作輸入薄膜電晶體以加強輸出波形的穩定性。因此，電路架構被簡化且單級佈局面積為400 μm × 126 μm。第二個電路為適用於大尺寸及高解析度之三維主動式有機發光二極體顯示器畫素電路，由三顆薄膜電晶體、一顆電容所組成。此電路利用同步式發光驅動法並可補償增強型及空乏型非晶相銦鎵鋅氧化物薄膜電晶體的臨界電壓漂移。根據模擬結果，當驅動薄膜電晶體的臨界電壓變異±1 V時，此電路的畫素電流相對誤差率在所有資料電壓範圍之內皆在4.46 %以下。第三個電路為適用於高解析度及高圖框頻率之藍相液晶顯示器畫素電路，由五顆薄膜電晶體、二顆儲存電容與一顆藍相液晶的等效電容所組成。藍相液晶的跨壓在其遭受頻率效應影響時仍可利用兩顆驅動薄膜電晶體維持在預期之電壓範圍，且施加其中一顆驅動薄膜電晶體閘極-源極反相偏壓以抑制臨界電壓的變異進而延長電路的使用壽命。模擬結果顯示，此電路在藍相液晶正極性及負極性時皆可正常操作。

In recent years, amorphous indium-gallium-zinc oxide thin-film transistors (a-IGZO TFTs) have gained considerable attention because they have better large-area uniformity, lower manufacturing cost and lower leakage currents than low-temperature polysilicon (LTPS) TFTs. Also, a-IGZO TFTs have higher mobility, better electrical stability and better transparency to visible light than do hydrogenated amorphous silicon (a-Si:H) TFTs. However, the threshold voltage shifts under gate voltage stress must be considered in design of gate driver circuits for active-matrix liquid crystal displays (AMLCDs) and pixel circuits for active-matrix organic light-emitting diode (AMOLED) and blue-phase (BP) LCDs, because they affect the lifetime of those circuits.
This thesis proposes three circuits that are based on a-IGZO TFTs, whose feasibility is verified by HSPICE simulations. The first circuit is a gate driver that comprises four TFTs and two capacitors and is suitable for high-resolution and narrow-bezel TFT-LCD applications. Three-phase overlapping clock signals with a 40% duty cycle are used to suppress the threshold voltage shifts of the a-IGZO TFTs. Furthermore, both the input TFT and the driving TFT provide paths for charging and discharging, reducing the number of components of the gate driver. Also, the input TFT can be made to enhance the stability of the output waveform by using an appropriate period of overlap of the clock signals. Consequently, the structure of the circuit is simplified and the resulting single-stage layout area is 400 μm × 126 μm. The second circuit is a pixel circuit that is composed of three TFTs and one capacitor and is for use in large-size and high-resolution three-dimensional (3D) AMOLED displays. The simultaneous emission (SE) driving scheme is utilized to provide enough time for shutter glasses to switch and reduces left-right crosstalk. The proposed pixel circuit for detecting the threshold voltage of the driving TFT is a source-follower structure to compensate for the threshold voltage shifts in both normally-off and normally-on a-IGZO TFTs. According to the simulation results obtained with ±1 V threshold voltage shifts of the driving TFT, the relative error rates of the OLED currents are less than 4.46% for the entire range of possible data voltages. The third circuit is a pixel circuit which consists five TFTs, two storage capacitors and one equivalent capacitor of the BPLC for high-resolution and high-frame-rate BP-LCDs. The voltage across the BPLC can be maintained by two driving TFTs when the BPLC suffers from the frequency effect. Moreover, the gate-source voltage in one of the driving TFTs is smaller than zero to ameliorate the threshold shifts of the a-IGZO TFTs and extend the lifetime of the proposed BPLC pixel circuit. Simulation results indicate that this circuit can operate with both positive polarity and negative polarity of the BPLC.

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