本篇論文主要探討一個十位元雙模式電流驅動式數位類比轉換器的設計、分析與實現。數位類比轉換器可分為數位部份及類比部分。在數位部分的設計是將六個最大位元(MSB)轉換成熱碼、四個最小位元(LSB)使用二位元碼, 以逹到較佳的差動非線性誤差(DNL)及確保電路的單調性(monotonicity)。在類比部分，電流單位可提供不同的電流以實現電壓或電流操作的功能。此外電源流的面積也經過適當的選擇以克服製程變動所造成的元件不匹配。電壓模式採用轉阻放大器將輸出電流透過電阻轉成電壓。電流模式則是直接驅動外掛電阻。此外也設計一個高速及低切換點的開關切換器來降低數位類比轉換器在切換過程中所造成的短時脈衝(glitch)的錯誤。
這個數位類比轉換器採用1P5M 0.25μm CMOS製程來實現。整個晶片核心面積是0.15 mm2,，與其它文獻相比較，這個晶片擁有最小面積。佈局後的模擬結果顯示此數位類比轉換器可操作在100MHz 轉換頻率。在電壓輸出模式時，當訊號頻率是7.8 MHz時，SNDR可以逹到59 dB。當訊號升到12.3MHz時，SNDR為56 dB。在電流輸出模式時，當訊號頻率是7.8 MHz時，SNDR可以逹到58.6 dB。當訊號升到12.3MHz時，SNDR為58 dB。

This thesis presents an investigation of the design, analysis, and implementation of 10-bit dual-mode current-steering DAC. The DAC is divided into a digital part and an analog part. In the digital part, the 6-bit MSB is converted into thermometer code and the binary weighted 4-bit LSB is used to get a better DNL error and guarantee monotonicity. In the analog part, the current cell that can provide of different currents is proposed. Thus, the current need to perform the voltage-mode or current-mode operation can be obtained. Besides, the area of current source is properly chosen to overcome mismatch error due to the process variation. A transimpedance amplifier is designed to convert current into voltage through resistor in voltage mode. The current mode DAC directly drives an external resistor. In addition, a high speed and low crossing point switch driver is designed to minimize glitch error during dynamic switching transition.
This DAC is fabricated with 0.25μm single-poly, five-metal process. The active area is 0.15 mm2 which is the smallest compared until those published up to now. The post-layout simulation shows that it can achieve 59/56 dB SNDR under a 100 MHz update rate with 7.8MHz/12.3MHz signal frequencies, respectively at voltage-mode operation. At the current-mode operation, the DAC can achieve 58.6/58 dB SNDR under the same condition with voltage mode.

[1] P.Hendriks, “Specifying communication DAC’s.” IEEE Spectrum, pp. 58-69, July 1997
[2] Anne Van den Bosch, Marc A. F.Borremans, Michel S. J. Steyaert and Willy Sansen, “A 10-bit 1-Gsample/s Nyquist Current-Steering CMOS D/A Converter”, IEEE J. Solid-State Circuits, vol. 36, pp. 315-324, Mar. 2001.
[3] Chi-Hung Lin and Klaas Bult, “A 10-b, 500-Msample/s CMOS DAC in 0.6 mm2”, IEEE J. Solid-State Circuits, vol. 33, pp. 1948-1958, Dec. 1999
[4] J. Bastos, Augusto M. Marques, M. Steyaert, and W. Sansen, “A 12-bit Intrinsic Accuracy High-Speed CMOS DAC”, IEEE J. Solid State Circuits, vol.33, No.12, pp.1959-1969, Dec. 1998
[5] Geert A. M. Van der Plas, Jan Vandenbussche, Willy Sansen, Michel S. J. Steyaert, and Georges G. E. Gielen, “A 14-bit Intrinsit Accuracy Q2 Random Walk CMOS DAC”, IEEE, J. Solid State Circuits, vol. 34, pp. 1708-1718, Dec. 1999.
[6] Alex R. Bugeja, Bang-Sup Song, Partrick L. Rakers, and Steven F. Gillig, “A 14-b, 100-MS/s CMOS DAC Designed for Spectral Performance” IEEE, J.Solid State Circuits, vol. 34, pp 1719-1732, Dec. 1999.
[7] Bruce J. Tesch and Juan C. Garcia, “A Low Glitch 14-b 100-MHz D/A Converter ”, IEEE J. Solid State Circuits, vol. 32, pp. 1465-1469, Sep. 1997.
[8] Alex R. Bugeja, and Bang-Sup Song, “A Self-Trimming 14-b 100-MS/s CMOS DAC”, IEEE J. Solid-State circuits, vol. 35, pp. 1841-1852, Dec. 2000.
[9] Shu-Yuan Chin and Chung-Yu Wu, “A 10-b 125-MHz CMOS Digital-to-Analog Converter (DAC) with Threshold-Voltage Compensated Current Sources”, IEEE J. Solid State Circuits, vol. 29, pp. 1374-1380, Nov. 1994.
[10] Yasuyuki Nakamura, Takahiro Miki, Atsushi Maeda, Harufusa Kondoh, and Nobuharu Yazawa, “A 10-b 70-MS/s CMOS D/A Converter”, IEEE J. Solid State Circuits, vol. 26, pp. 637-642, April 1991.
[11] D. Wouter J. Groeneveld, Hans J. Schouwenaars, Henk A.H. Termeer, and Cornelis A. A. Bastiaansen, “A Self-Calibration Technique for Monolithic High-Resolution D/A Converters”, IEEE J. Solid State Circuits, vol. 24, pp.1517-1522, Dec. 1989.
[12] B.Razavi, “Principles of Data Conversion System Design,” NJ: IEEE Press, 1995.
[13] Mikael Gustavsson, J.Jacob Wikner, and Nianxiong Nick Tan, “CMOS data converters for communications,” Boston, 2000.
[14] David A. Johns and Ken Martin, “Analog Integrated Circuit Design,” John Wiley & Sons Inc, 1997.
[15] Behzad Razavi, “Design of Analog CMOS Integrated Circuits,” McGraw-Hill, 2001
[16] Katayoun Falakshahi, “High Speed High-Resolution D/A Conversion in CMOS,” Ph.D. Dissertation, Standford University, March. 1999.
[17] Jose Bastos, “Characterization of MOS Transistor Mismatch for Analog Design,” Ph.D. Dissertation, Katholieke University Leuven, April 1998.
[18] C. Bastiaansen, D. Groeneveld, H. Schouwenaars, and H. Termeer, “A 10-b 40-MHz 0.8-μm CMOS current-output D/A converter,” IEEE J. Solid-State Circuits, vol. 26, no.7, pp. 917-921, July 1991.
[19] A. Cremonesi, F. Maloberti, and G.. Polito, “A 100-MHz CMOS DAC for video-graphic systems,” IEEE J. Solid-State Circuits, vol. 24, no. 3, pp. 635-639, June 1989.
[20] J. Fournier and P. Senn, “A 130 MHz 8-bit CMOS video DAC for HDTV applications,” IEEE J. Solid-State Circuits, vol. 26 no. 7, pp. 1073-1077, July 1991.
[21] D. Mercer, “A 16-b D/A Converter with increased spurious free dynamic range, ” IEEE J. Solid-State Circuits, vol. 29, no. 10, pp. 1180-1181, Oct. 1994.
[22] T. Wu, C. Jih, J. Chen, and C. Wu, “A low glitch 10-bit 75-MHz CMOS video D/A Converter,” IEEE J. Solid-State Circuits, vol. 30, no. 1, pp. 68-72, Jan. 1995.
[23] Jan M. Rabaey, “Digital Integrated Circuits,” Prentice Hall, Inc. 1996.
[24] M. J. M. Pelgrom et. al. “Matching properties of MOS transistors”, IEEE, J. Solid State Circuits, vol. 24, pp. 1433-1439, Oct.1989.
[25] ”Design Documents for TSMC 0.25um 1P5M Mixed Signal Process”