本論文旨在研究用於電漿製程之射頻阻抗匹配器，藉由偵測射頻電源端之輸入阻抗是否達匹配情況，進行其功率匹配狀態偵測電路設計。文中提出偵測頻率為13.56MHz的功率偵測電路係以輸出阻抗50歐姆為匹配情況作設計，依數位式阻抗匹配器其電控流程於匹配狀態所需偵測資訊，將射頻功率偵測機制分為前端功率擷取電路、振幅偵測、相位偵測、反射功率偵測電路。功率擷取電路係以比流器及分壓電路實現；振幅偵測部份，本文提出三種偵幅偵測電路架構，最後採用單端式功率偵測器；相位偵測係用高速比較器與數位邏輯判斷電路組成，最後以VSWR概念的雙定向耦合器橋式架構作反射功率偵測電路設計。經實驗測試，所設計之電路可確實達射頻電壓及電流訊號之振幅峰值偵測、其相位差及相位領先及落後判斷及系統反射功率偵測之功能，最後將射頻訊號資訊轉成直流電壓訊號作A/D轉換，以提供數位式射頻阻抗匹配器MCU的輸入功率匹配資訊，作為調整匹配網絡依據，以避免反射功率的發生。

The purpose of this thesis is to present a radio frequency (RF) power matching state detector of impedance matching box for plasma chamber. The thesis proposed RF power detecting mechanism designing at 13.56 MHz as the impedance is 50 ohms called matching state. The main feature of the proposed RF power detecting mechanism is split the power signal into voltage and current signal, subsequently detecting their magnitude and phase information. The method of this function comprise data acquisition circuit made by voltage divider and current transformer; magnitude detecting function which is realized by power detector; phase detecting part is composed of high speed digital logic gates circuit. Moreover, the reflected power signal is detected by the conception of VSWR meter, restructuring of directional coupler, is the last step to verify the system conform to the impedance matching condition and transform these signals into power matching state information through ADC function of MCU. By means of the circuit simulation and experimental results to prove the feasibility of proposed RF power signal detection function.

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