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研究生：	何政勳 Ho, Cheng-Hsun
論文名稱：	一個基於固定時間視窗的十位元每秒取樣十萬次低功率逐漸趨近式類比至數位轉換器 A 10-bit 100-kS/s Low Power SAR ADC with Time-based Fixed Window
指導教授：	張順志 Chang, Soon-Jyu
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 電機工程學系 Department of Electrical Engineering
論文出版年：	2012
畢業學年度：	100
語文別：	英文
論文頁數：	97
中文關鍵詞：	逐漸趨近式類比至數位轉換器、逐漸趨近式、類比至數位轉換器、低功率
外文關鍵詞：	SAR ADC, SAR, ADC, low power
相關次數：	點閱：78 下載：8
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本論文實現了一個基於固定時間視窗的十位元每秒取樣十萬次低功率逐漸趨近式類比至數位轉換器。藉由此視窗的輔助，所研製之逐漸趨近式類比至數位轉換器避免了不必要的電容切換、比較次數和數位控制操作。因此，其功率消耗可有效地被降低。除此之外，本論文提出了新型之三維單位電容與網狀式電容陣列，可降低面積以及總電容值。經由量測驗證，此新電容可達到10位元的精確度。
本設計的類比至數位轉換器使用台積電0.18微米製程，其核心電路的面積為178 × 184 平方微米。在0.5伏特供應電壓與每秒十萬次的取樣下，功率消耗為252.2奈瓦。在1千赫茲的輸入訊號下，得到的訊號雜訊失真比、無雜訊影響動態範圍分別為57.96分貝和68.70分貝。有效位元數為9.34位元。微分非線性誤差峰值、積分非線性誤差峰值分別為+0.39/-0.39 最低有效位元和+0.71/-0.59最低有效位元。每一次資料轉換所消耗的能量只有3.89費焦耳。

This thesis presents a 10-bit 100-kS/s low power SAR ADC with time-based fixed window. The unnecessary capacitor switching, and their corresponding, comparisons and digital control operations, are avoided under the assistance of the fixed window technique. Therefore, the power consumption can be significantly reduced. In addition, this ADC proposes a novel 3-dimensional unit capacitor and a meshed capacitor array, resulting in a small total capacitance and area. The measurement results indicate this new capacitor structure can achieve an accuracy of 10-bit.
The designed ADC occupies an active area of only 178 × 184 m2 in 0.18-m CMOS process. At 0.5-V supply and 100-kS/s, the ADC consumes only 252.2 nW. The SNDR and SFDR at 1-kHz input frequency are 57.96 dB and 68.70 dB, respectively. The ENOB is 9.34 bits. The peak DNL and INL are +0.39/-0.39 LSB and +0.71/-0.59 LSB, respectively. The FOM is only 3.89 fJ/c.-step.

List of Tables VII
List of Figures VIII

Chapter 1 Introduction 1
1 Motivation 1
2 Thesis Organization 4

Chapter2 Fundamentals of Analog-to-Digital Converter (ADC) 5
1 Introduction 5
2 ADC Performance Metrics 6
2.1 Resolution and Accuracy 6
2.1.1 Resolution 6
2.1.2 Accuracy 7
2.2 Static Performance 7
2.2.1 Offset Error 7
2.2.2 Gain Error 8
2.2.3 Nonlinearity 9
2.3 Dynamic Performance 12
2.3.1 Signal-to-Noise Ratio 12
2.3.2 Signal-to-Noise Distortion Ratio 15
2.3.3 Effective Number of Bits 16
2.3.4 Spurious Free Dynamic Range 16
2.3.5 Total Harmonic Distortion 17
2.3.6 Figure-of-Merit (FOM) 17
3 Review of ADC Architectures	18
3.1 Flash ADC	19
3.2 Two-Step ADC 20
3.3 Pipelined ADC 22
3.4 Cyclic ADC (or Algorithmic ADC) 24
3.5 Time-Interleaved ADC 25

Chapter 3 Successive Approximation Register (SAR) ADC 27
1 Introduction 27
2 Architecture of SAR ADC 28
2.1 DAC-Based SAR ADC	28
2.2 Charge-Redistribution ADC	31
3 Asynchronous Processing 35
4 Energy-Efficient Capacitor Switching Sequence 38
4.1 Conventional Capacitor Switching Sequence	38
4.2 Split Capacitor Switching Sequence 40
4.3 Monotonic Capacitor Switching Sequence 43
4.4 Vcm-Based Capacitor Switching Sequence 45
4.5 Partial Floating Capacitor Switching Sequence 47
4.6 Summary of Capacitor Switching Sequences 49
5 The Principle of Variable Window Function 49
5.1 Splitting Monotonic Capacitor Switching Sequence 51
5.2 The Concept and Circuit Implementation of Window Function 53

Chapter 4 A 10-bit 100-kS/s Low Power SAR ADC with Time-based Fixed Window 56
1 Introduction 56
2 Architecture and Operation 56
3 Circuit Implementation 59
3.1 Sample and Hold Circuit 59
3.2 Dynamic Two-Stage Comparator 63
3.3 Digital-to-Analog Converter 65
3.4 Time-Level Decision Circuit 68
3.5 Timing Controller 70
3.6 DAC Control Logic (or SAR Control Logic) 74
3.7 Code-Recovery Circuit 75
4 Simulation Results of 10-bit 100-kS/s SAR ADC 76
5 Measurement Setup 83
6 Measurement Results of 10-bit 100-kS/s SAR ADC 84

Chapter 5 Conclusion and Future Work 92

Bibliography 94
                                    

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校內：2017-08-27公開
校外：2017-08-27公開

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