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研究生：	張詠翔 Jhang, Yong-Siang
論文名稱：	利用選擇性蝕刻技術改善堆疊式奈米線電晶體之性能 Performance Improvement On Stacked Nanowire Transistor Using Selective Etching Technique
指導教授：	李文熙 Lee, Wen-Shi
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 電機工程學系 Department of Electrical Engineering
論文出版年：	2020
畢業學年度：	108
語文別：	英文
論文頁數：	60
中文關鍵詞：	矽鍺、乾蝕刻、堆疊式環繞電晶體、側向蝕刻、蝕刻選擇比、四氟化碳
外文關鍵詞：	silicon germanium, dry etching, stacked gate all around transistor, lateral etching, selectivity etching ratio, carbon tetrafluoride
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隨著半導體元件尺寸持續微縮而出現了不可忽視的短通道效應，傳統上，隨著通道長度的縮小，採用更高濃度的參雜與較薄的閘極介電質，來改善閘極的控制並增強性能。但是，這些技術正接近材料與製程的極限，其中一種是傳統的平面電晶體的結構從 20nm，7nm 縮小到現在的 2nm 結構，其漏電流已經嚴重影響電晶體的性能，而後來開發的 finFET 有稍微的改善漏電流問題，但這還不夠，因此，尋找新的結構變得更加重要。基本上漏電流的出現與閘極有極大的關係，在finFET 的結構中閘極只圍繞了三個面，最後的面就會造成漏電流，因此出現了一種新型的結構，他的四個側面都被閘極包覆著，將其稱為閘極環繞式電晶體，以下將以 GAA 來代稱，通過增加閘極的控制面積，將可以更好地減少漏電流的問題。此外 GAA 的製程單純，對於在原件上的設計更具彈性，可藉由增加鰭片的寬度以增加電流，或減少寬度限制功耗，故本實驗希望能夠在使用感應式耦合電漿系統研究其流量對蝕刻速率與輪廓影響之探討。
本論文主要使用感應耦合電漿系統來作研究，首先將蝕刻參數應用在矽基板上，分別使用不同流量的四氟化碳(CF4)和偏壓(Bias)，對其做討論，選擇較高的蝕刻率與較好的蝕刻輪廓後。把參數帶入研究半導體堆疊式新型結構-矽/矽鍺/矽，以超高真空化學氣象沉積(UHVCVD)磊晶不同比例的矽鍺薄膜後，在矽鍺薄膜上磊晶矽薄膜形成堆疊式結構，對其使用不同參數下的感應耦合電漿系統進行蝕刻，觀察側向蝕刻，並且找出最佳的蝕刻選擇比以優化堆疊式結構。

Continued miniaturization of bulk silicon CMOS ransistors is being limited by degrading short channel effects. Traditionally, higher channel doping, shallower source/drain junctions, and thinner gate dielectrics have been employed to improve gate control and enhance performance as the gate length is scaled down. However, these techniques are rapidly approaching material and process limits. Alternate transistor on semiconductor technologies, of which one of the traditional planar transistor’s structure shrinkage from 20nm,7nm and now 2nm dimension regime, there is a cause in current leakage which cannot be ignored anymore. Thereby finFET was developed subsequently to improve the leakage current, but it was not enough. Therefore, finding some new structures had become more important. Basically, the structure of finFET surrounds three sides of the gate, the last side of the gate is one which is not might have
some leakages, so a new type of structure has developed that appears with other fourth sides surrounded “stacked gate all around”, and which will be referred to by its
abbreviation GAA later. By increasing the controlled area of gate toward channel, we are able to control the leakage better.
In addition to, the manufacturing process is simple, which gives us more flexibility while designing the devices. We can enhance the current by increasing the width of fins,or decrease the width to limit the power consumption. Thus, this experiment is trying
to find out the relation between flowrate, auxiliary gas and the figure out etching rate and its profile under the premise of using inductive couple plasma system.
The research of this thesis uses inductively coupled plasma (ICP) system as the main equipment. First, by trying different flowrate, bias and pressure of carbon
tetrafluoride on silicon substrate, we find out some parameters which gives better etching rates and etching profile. Second, we construct a stacked structure of silicon germanium layer in the middle of silicon layers, using the technology Ultra-High Vacuum Chemical Vapor Deposition. And then applied the previous result to conduct etching experiments on those stacked substrates with the ICP system.
we analyze the lateral etching and figure out the best selectivity etching ratio to improve the etching process of stacked structure MOSFETs.

摘要 …………………………………………………………………………i 
ABSTRACT……………………………………………………………… ii 
致謝 ………………………………………………………………………….iv 
LIST OF FIGURES ………………………………………………………………………… vii 
LIST OF TABLES ………………………………………………………………………… x 
Chapter 1 Introduction ………………………………………………………………………… 1 
1 Background …………………………………………………………………………1 
2 Scope of this study ………………………………………………………………………… 3 
3 Research Motivation ………………………………………………………………………… 3 
4 Research Objective………………………………………………………………………… 4 
5 Thesis Overview ………………………………………………………………………… 5 
Chapter 2 Literature Review ……………………………………………………………………… 6 
1 Introduction to Gate-All-Around (GAA) Transistor ………………………………………………………………………… 6 
2 Short Channel Effects ………………………………………………………………………… 7 
3 Concept of Selective Etching Technique………………………………… 9 
3.1 Selective Etching ………………………………………………………………………… 9 
3.2 Plasma etching ………………………………………………………………………… 9 
4 Inductively Coupled Plasma ……………………………………………………………13 
Chapter 3 Experimental Techniques ………………………………………………………16 
1 Equipment Utilized …………………………………………………………………………16 
1.1 Four-inch Inductively Coupled Plasma Etching Machine ………………………………………………………………………… 16 
2 Substrate Preparation Instruction ……………………………………………18 
2.1 Sample Details ………………………………………………………………………… 18 
2.2 Four- group epitaxial ……………………………………………………………… 18 
3 Process Flow …………………………………………………………………………19 
4 Experimental Procedure …………………………………………………………………………21 
4.1 Sample preparation and Cleaning………………………………………………21 
4.2 Photoresist Patterning ………………………………………………………………… 21 
4.3 Inductively Coupled Plasma etching silicon substrate ………………………………………………………………………… 22 
4.4 Inductively Coupled Plasma etching Stacked structure ………………………………………………………………………… 22 
Chapter 4 Results and Discussion………………………………………………………… 25 
1 Etching effect on silicon substrate ………………………………………25 
1.1 Effect of bias voltage ………………………………………………………………… 25 
1.2 Etching effect of different carbon tetrafluoride flow rate………………………………………………………………………… 27 
2 Etching effects under various pressure condition on Si1-xGex substrate 
material …………………………………………………………………………31 
2.1 Samples preparation on 50 nm width different Sacrificial layer Si1-xGex 
layer and Si layer ………………………………………………………………………… 31 
2.2 Etching under different pressure …………………………………………34 
2.3 Optimization of Etching Time ………………………………………………… 49 
3 Fabrication of Gate-All-Around Structure …………………………51 
Chapter 5 Conclusion and Future Work …………………………………………… 56 
1 Conclusion …………………………………………………………………………56 
2 Future work …………………………………………………………………………57 
Reference …………………………………………………………………………58 
                                    

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校內：2025-08-31公開
校外：不公開電子論文尚未授權公開，紙本請查館藏目錄

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