應用無線之方式進行通訊以及偵測是現今相當重要之技術，且於生醫領域方面，此種技術更是極為常見。本論文首先提出一個應用電路之整流與非線性元件特性所產生之二次諧波進行人體胸腔呼吸起伏之偵測之自供電式射頻標籤設計，利用偶極天線擷取外部傳入之 2.4 GHz 射頻訊號，經過一差動變壓器與全波整流器後產生二次諧波項，再利用直接注入鎖定之方式控制後方 TITO 型振盪器之輸出頻率，使其振盪於輸入射頻訊號之兩倍，再經過一級輸出緩衝級後，藉由天線將訊號射出，以達偵測人體胸腔起伏之功效。

接著，本論文繼續提出應用此自供電之射頻標籤來當作參考時脈源之 4.8 GHz 鎖相迴路之設計。此設計採用互補式 LC 型壓控震盪器搭配三位元之切換電容陣列以增加其頻率可調範圍，搭配電流邏輯式除頻器以及多模數除頻器完成鎖相迴路端之除頻串，此端也包括可消除突波之相位頻率偵測器，以回授控制與疊接方式增加電流匹配度之電荷幫浦，以及二階之被動迴路濾波器。參考時脈源端則是使用射頻標籤以提供 2.4 GHz 附近之頻率，再利用真實單相位時脈除頻器以及多模數除頻器來進行降頻，以當鎖相迴路之參考頻率之用。

最後，為了改善自供電之射頻標籤在量測上發現的 TITO 型振盪器之自振強度較弱之問題，且也希望可以有更佳之數據表現，又進行了此電路之調整並再次下線。主要差別在於其輸出端之緩衝級設計，在此進行強化以期能夠有效提高輸出訊號之功率，使 TITO 型振盪器在自振時各項特性之量測得以更加順利。且在 TITO 型振盪器之電感 Q 值的選擇上，以及整體振盪器核心之面積也都有進行優化，以有效提高振盪器自振強度與鎖定頻寬。

以上所述之所有晶片電路皆是使用台積電所提供之 TSMC 0.18-μm CMOS 製程。且本論文將依序詳細介紹以上晶片之電路架構以及其模擬與量測結果。

Applications of wireless communication and detection has been pretty important nowadays, which is also universal in bio-medical field. Therefore, this thesis in the first part proposes a self-powered RF tag using the properties of rectification and nonlinearity to generate the second-harmonic in order to achieve human ribcage respiratory movements detection. The second-harmonic of the 2.4 GHz RF signals harvested by a dipole antenna can be peaked by a differential transformer and a full-wave rectifier and injected into the following TITO (tuned-input tuned-output) oscillator to control its output frequencies oscillating at exactly the second-harmonic of the input frequencies harvested by the dipole antenna. Then the output frequencies are fed into one buffer stage and the following antenna receives the outputs of this buffer stage and emits them out to accomplish the human ribcage respiratory movements detection.

Furthermore, this thesis also proposes a 4.8 GHz PLL design utilizing the self-powered RF tag as the reference clock source. A complementary LC VCO (voltage-controlled oscillator) is used in the design with 3-bit switched-capacitor binary-weighted arrays for the expansion of the frequency tuning range. And the following divider chain consists of two CMLs (current-mode logic dividers), and a MMFD (multi-modulus frequency divider). Besides, A PFD (phase-frequency detector) with glitch rejection ability, a charge pump with dynamic feedback control and cascode techniques for better current matching and a second-order passive loop filer are included as well. In addition, the self-powered RF tag generating signals with frequencies around 2.4 GHz is included in the part of reference clock source. And then the frequencies of the signals from this RF tag are divided down for the purpose of the reference clock source by the following TSPC (true single phase clock) dividers and a MMFD.

Finally, in order to improve the problems of the TITO oscillator in the self-powered RF tag in the first design that its self-oscillation ability is not strong enough for better performance in the measurement, the re-tapeout of this design has been done with some adjustments such as the enhancement of the output buffer stages and the Q value of this oscillator. The output buffer stages are radically changed for higher output power and moreover better Q value and more compact core layout are chosen and achieved, respectively. Therefore, much stronger self-oscillation ability and much wider input frequency range can be accomplished. In addition, all designs mentioned above are all fabricated by TSMC 0.18-μm CMOS process.

[1] A. Singh, “Respiratory monitoring and clutter rejection using a CW Doppler radar with passive RF tags,” IEEE Sensor Journal, vol. 12, no. 3, pp. 558-565, Mar. 2012
[2] F. Kocer, P. M. Walsh and M. P. Flynn, “An RF powered, wireless temperature sensor in quarter micron CMOS,” ISCA '04, Proceeding of the International Symposium on Circuits and Systems, vol. 4, pp. IV-876-9, May 2004
[3] F. Kocer and M. P. Flynn, “An RF-powered, wireless CMOS temperature snesor,” IEEE Sensor Journal, vol. 6, no. 3, pp. 557-564, Jun. 2006
[4] J. F. Dickson, “On-chip high-voltage generation in MNOS integrated circuit using an improved voltage multiplier technique,” IEEE Journal of Solid-State Circuits, vol. 11, no. 3, pp. 374-378, Jun. 1976
[5] A. Costantini, B. Lawrence, S. Mahon, J. Harvey, G. McCulloch and A. Bessemoulin, “Broadband active and passive balun circuits: Functional blocks for modern millimeter-wave radio architectures,” The 1st European Microwave Integrated Circuits Conference, pp. 421-424, 10-13 Sept. 2006
[6] A. A. Kidwai, A. Nazimov, Y. Eilat and O. Degani “Fully integrated 23dBm transmit chain with on-chip power amplifier and balun for 802.11a application in standard 45nm CMOS process,” IEEE Radio Frequency Integrated Circuits Symposium, pp. 273-276, 7-9 Jun. 2009
[7] D. V. Vorst and S. Mirabbasi “Low-power 1V 5.8 GHz bulk-driven mixer with on-chip balun in 0.18μm CMOS,” IEEE Radio Frequency Integrated Circuits Symposium, pp. 197-200, Jun. 17-Apr. 17 2008
[8] G. Felic and E. Skafidas, “An integrated transformer balun for 60 GHz silicon RF IC design,” International Symposium on Signals, Systems and Electronics, pp. 541-542, Jul. 30-Aug. 2 2007
[9] C.-H. Huang, C.-H. Chen and T.-S. Horng, “Design of Marchan balun of spiral shape using physical transformer model on silicon integrated passive device substrate,” IEEE Radio and Wireless Symposium, pp. 456-459, 10-14 Jan. 2010
[10] M. Peng, M. Lin, T. W. Shi and F. F. Dai, “A 2.4GHz front-end with on-chip balun in a 0.13um CMOS technology,” IEEE International Conference on Solid-State and Integrated Circuit Technology, pp. 512-514, 1-4 Nov. 2010
[11] M. Goldfard, J. B. Cole and A. Platzker, “A novel MMIC biphase modulator with variable gain using enhancement-mode FETS suitable for 3 V wireless applications,” IEEE Microwave and Millimeter-Wave Monolithic Circuits Symposium, Digest of Papers, pp. 99-102, 22-25 May 1994
[12] H. Koizumi, S. Nagata, K. Tateoka, K. Kanazawa, D. Ueda, “A GaAs single balanced mixer MMIC with built-in active balun for personal communication system,” IEEE Microwave and Millimeter-Wave Monolithic Circuits Symposium, Digest of Papers, pp. 77-80, 15-16 May 1995
[13] L. M. Devlin, B. J. Buck, J C. Clifton, A. W. Dearn and A. P. Long, “A 2.4 GHz single chip transceiver,” IEEE Microwave and Millimeter-Wave Monolithic Circuits Symposium, Digest of Papers, pp. 23-26, 1993
[14] M. huainan, S. J. Fang, F. Lin, K.-S. Tan, J. Shibata, A. Tamura and H. Nakamura, “A high performance GaAs MMIC upconverter with an automatic gain control amplifier,” Gallium Arsenide Integrated Circuit Symposium, Technical Digest, 19th Annual, pp. 232-235, 12-15 Oct. 1997
[15] Y. Xuan and J. I. Fikart, “Computer-aided design of microwave frequency doublers using a new circuit structure,” IEEE Transactions on Microwave Theory and Technique, vol. 41, no. 12, pp. 2264-2268, Dec. 1993
[16] W. H. Hayward and S. S. Taylor, “Compensation method and apparatus for enhancing single ended to differential conversion,” United States Patent, Nov. 26 1991
[17] T.-T. Hsu and C.-N. Kuo, “Low power 8-GHz ultra-wideband active balun,” Topical Meeting on Silicon Monolithic Integrated Circuits in RF Systems, Digest of Papers, 18-20 Jan. 2006
[18] G. Papottom, F. Carrara and G. Palmisano, “A 90-nm CMOS threshold-compensation RF energy harvester,” IEEE Journal of Solid-State, vol. 46, no. 9, pp. 1985-1997, Sept. 2011
[19] H. Nakamoto, D. Yamazaki, T. Yamamoto, H. Kurata, S. Yamada, K. Mukaida, T. Ninomiya, T. Ohkawa, S. Masul and K. Gotoh, “A passive UHF identification CMOS tag IC using ferroelectric RAM in 0.35-μm technology,” IEEE Journal of Solid-State, vol. 42, no. 1, pp. 101-110, Jan. 2007
[20] T. Le, K. Mayaram and T. Kiez, “Efficient far-field radio frequency energy harvesting for passively powered sensor networks,” IEEE Journal of Solid-State, vol. 43, no. 5, pp. 1287-1302, May 2008
[21] B. Razavi, “Fundamentals of microelectronics,” Wiley, 2007
[22] G. Papotto, F. Carrara and G. Palmisano, “A 90-nm CMOS threshold-compensated RF energy harvester,” IEEE Journal of Solid-State, vol. 46, no. 9, pp. 1985-1997, Sept. 2011
[23] M. T. Penella-Lopez, M. Gasulla-Forner, “Powering autonomous sensors,” Spinger, 2011
[24] T. Umeda, H. Yoshida, S. Sekine, Y. Fujita, T. Suzuki and S. Otaka, “A 950-MHz rectifier circuit for sensor network tags with 10-m distance,” IEEE Journal of Solid-State, vol. 41, no. 1, pp. 35-41, Jan. 2006
[25] W. A. Edson, “Vacuum-tube oscillators,” New York: John Wiley & Sons, Inc., 1953.
[26] S. Shekhar, S. Aniruddhan and D. J. Allstot, “A tuned-input tuned-output VCO in 0.18μm CMOS,” IEEE Radio Frequency Integrated Circuits Symposium, pp. 607-610, 3-5 Jun. 2007
[27] S. Shekhar, j. S. Walling, S. Aniruddhan and D. J. Allstot, “CMOS VCO and LNA using tuned-input tuned-output circuits,” IEEE Journal of Solid-State, vol. 43, no. 5, pp. 1177-1186, May 2008
[28] D. J. Allstot, S. Aniruddhan, M. Chu, N. M. Neihart, D. Ozis, S. Shekhar and J. S. Walling, “Low phase noise CMOS voltage-controlled oscillators,” 7th International Conference on ASIC, pp. 297-302, 22-25 Oct. 2007
[29] T. N. Nguyen and J.-W. Lee, “A low phase noise PMOS tuned-input tuned-output voltage controlled oscillator in 0.18 μm CMOS technology,” IEEE Microwave and Optical Technology Letters, vol. 52, no. 8, pp. 1852-1855, Aug. 2010
[30] A. Dec, K. Suyama and T. kitamura, “A 4.5 GHz LC-VCO with self-regulating technique,” IEEE International Solid-State Circuits Conference, Digest of Technical Papers, pp. 90-589, 11-15 Feb. 2007
[31] Y.-J. Wang, X.-N. Fan and B. Li, “A 0.18μm 1 V 5GHz LC VCO designed for WSN applications,” IEEE 11th International Conference on Solid-State and Integrated Circuit Technology, pp. 1-3, Oct. 29-Nov. 1 2012
[32] A. Lacaita, S. Levantino and C. Samori, "Integrated frequency synthesizers for wireless systems, " Cambridge, 2007
[33] H.-T. Lin, “Research on CMOS RF MEMS switches and 2-GHz/5-GHz VCO RFICs for wireless communication applications,” Master, Department of Electrical Engineering, National Cheng Kung University, Tainan City, 2004
[34] W.-S. Su, “Designs of sensor oscillator, PLL, and frequency-to-voltage converter for non-invasive IOP measurement systems,” Master, Department of Electrical Engineering, National Cheng Kung University, Tainan City, 2011
[35] J. Roger, C. Plett and F. Dai, “Integrated circuit design for high speed frequency synthesis, ” Archtech House, 2006
[36] B. Razavi, “Design of analog CMOS integrated circuit,” McGRAW Hill International edition, 2001
[37] A. A. M. Ismail, “CMOS PLL and VCOs for 4G wireless,” Kluwer Academic Publishers, 2004
[38] J. Craninckx and M. Steyaert, “Wireless CMOS frequency synthesizer design,” Kluwer Academic Publishers, 1998
[39] Y.-C. Chang, “Design of CMOS frequency synthesizer for electromagnetic micro-motion detection system,” Master, Department of Electrical Engineering, National Chung Cheng University, Chiayi, 2007
[40] K. Shu and E. S. Sinensio, “CMOS PLL frequency synthesizers analysis and design,” Springer, 2005
[41] C.-M. Hung and K. K. O, “A fully integrated 1.5-V 5.5-GHz CMOS phase-locked loop,” IEEE Journal of Solid-State, vol. 37, no. 4, pp. 521-525, Apr. 2002
[42] W.-H Lee, J.-D. Cho and S.-D. Lee, “A high speed and low power phase-frequency detector and charge-pump,” Design Automation Conference, Proceeding of the ASP-DAC '99, pp. 269-272, 18-21 Jan. 1999
[43] J.-S. Lee, M.-S. Keel, S.-I. Lim and S. Kim, “Charge pump with perfect current matching characteristics in phase-locked loops,” Electronic Letters, vol. 36, no. 23, pp. 1907-1908, 9 Nov. 2000
[44] T.-H. Lin, C.-L. Ti and Y.-H. Liu, “Dynamic current-matching charge pump and gated-offset linearization technique for delta-sigma fractional-N PLLs,” IEEE Transactions on Circuits and Systems-I : Regular Papers, vol. 56, no. 5, pp. 877-885, May 2009
[45] 高曜煌，射頻鎖相迴路 IC 設計，滄海書局，2005
[46] F. M. Gardner, “Charge-pump phase-locked loops,” IEEE Transactions on Communications, vol. 28, no. 11, pp. 1849-1858, Nov. 1980
[47] J. S. Pak, J. Kim, D. H. Jung, J. Lee, K. Park and J. Kim, “Optimized inverter design of ring oscillator based wafer-level TSV connectivity test (RO-TSV-CT),” IEEE Electronic Design of Advanced Packaging and Systems Symposium, pp. 239-242, 9-11 Dec. 2012
[48] S. S. Mohan, W. S. Chan, D. M. Colleran, S. F. Greenwood, J. E. Gamble and I. G. Kouznetsov, “Differential ring oscillators with multipath delay stages,” IEEE Conference Integrated Circuits Conference, pp. 503-506, 18-21 Sept. 2005
[49] 劉深淵，楊清淵，鎖相迴路，滄海書局，2006
[50] A. Hajimiri and T. H. Lee, “Design issues in CMOS differential LC oscillators,” IEEE Journal of Solid-State, vol. 34, no. 5, pp. 717-724, May 1999
[51] S. Zhenhua and Li Zhiqun, “Design of a low-power high-speed CMOS frequency divider for WSN applications,” IEEE 13th International Conference on Communication Technology, pp. 1091-1094, 25-28 Sept. 2011
[52] T. Fuse, M. Tokumasu, S. Kawanaka, H. Fujii, A. Kameyama, M. Yoshimi and S. Watanabe, “A 1.1 V SOI CMOS frequency divider using body-inputting SCL circuit technology,” IEEE International SOI Conference, pp. 106-107, 2000
[53] J. Yuan and C. Svensson, “High-speed CMOS circuit technique,” IEEE Journal of Solid-State, vol. 24, no. 1, pp. 62-70, 1989
[54] N. H. E. Weste, D. Harris, “CMOS VLSI design-a circuit and systems perspective, ” Addition Wesley, 3rd ed. 2005
[55] H.-H. Chang and J.-C. Wu, “A 723-MHz 17.2-mW CMOS programmable counter,” IEEE Journal of Solid-State, vol. 33, no. 10, pp. 1572-1575, Oct. 1998
[56] S.-H. Lee and H. J. Park, “A CMOS high-speed wide-range programmable counter,” IEEE Transactions on Circuits and Systems-II : Analog and Digital Signal Processing, vol. 49, no. 9, pp. 638-642, Sept. 2002
[57] W.-J. Lee, “CMOS delta-sigma frequency synthesizer design for 802.11a transceiver,” Master, Department of Electronics and Electro-Optical Engineering, National Chiao Tung University, Hsinchu, 2004
[58] Z.-B. Lou, “The fractional-N nonlinearity study and mixed-mode IC implementation of frequency synthesizers,” Master, Department of Electrical Engineering, National Sun Yat-Sen University, Kaohsiung City, 2006
[59] S. Pellerano, S. Levantino, C. Samori and A. L. Lacaita, “A 13.5-mW 5-GHz frequency synthesizer with dynamic-logic frequency divider,” IEEE Journal of Solid-State, vol. 39, no. 2, pp. 378-383, Feb. 2004
[60] W.-H. Chiu, T.-S. Chan and T.-H. Lin, “A 5.5-GHz 16-mW fast-locking frequency synthesizer in 0.18-μm CMOS,” IEEE Asian Solid-State Conference, pp. 456-459, 12-14 Nov. 2007
[61] P.-Y. Deng and J.-F. Kiang, “A 5-GHz CMOS frequency synthesizer with an injection-locked frequency divider and differential switched capacitors,” IEEE Transactions on Circuits and Systems-I : Regular Papers, pp. 320-326, 12-14 Feb. 2009