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研究生： 簡銘宏
Chien, Ming-Hung
論文名稱： 一個採用雙二進制編碼的低功率電壓模式發射器
A Low Power Duobinary Voltage-Mode Transmitter
指導教授： 張順志
Chang, Soon-Jyh
學位類別： 碩士
Master
系所名稱： 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年： 2017
畢業學年度： 106
語文別： 英文
論文頁數： 86
中文關鍵詞： 電壓模式發射器 、雙二進制編碼 、有線傳輸
外文關鍵詞： Voltage-Mode Transmitter, Duobinary, Wireline Communication
相關次數： 點閱：90  下載：16 
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    • 本論文呈現一個應用於有線傳輸且採用雙二進制編碼的低功率電壓模式發射器。藉由控制差動輸出之間的路徑，所提出的雙二進制控制方法把傳統的不歸零電壓模式發射器輕易的轉換成雙二進制電壓模式發射器；同時提出新的預加強方法來克服有頻率相依特性的通道損失，並包含阻抗匹配技巧來維持訊號的完整性。
    此雙二進制編碼的電壓模式發射器以台灣積體電路公司的90奈米互補式金屬氧化物半導體製程進行設計與製作，在輸入資料頻率為6 Gbps下，以偽亂數二進位數列15的模式輸入，並且設定2.16 dB的預加強增益下，經過20公分的FR4板子通道及90公分的電纜線後，輸出眼高為109.375 mV，眼寬為47.301 ps，而抖動的方均根值為17.14 ps，此測試晶片的核心電路面積以及功耗效率值分別為0.066 mm2和2.36 pJ/bit。

    The thesis presents a low power duobinary voltage-mode transmitter for wireline communication. By controlling a short path between two differential terminals, the proposed duobinary control scheme can easily transform a conventional NRZ voltage-mode transmitter into a duobinary voltage-mode transmitter. Meanwhile, a new pre-emphasis method, including a common impedance matching technique, is proposed to overcome frequency-dependent channel loss and maintain signal integrity.
    The duobinary voltage-mode transmitter is designed and fabricated in TSMC 90-nm CMOS process. The measured data eye height is 109.375 mV, eye width is 47.301 ps and RMS jitter is 17.14 ps with a pseudo random binary sequence (PRBS) 15 pattern at 6Gb/s and 1-V supply voltage at the far end of 20-cm FR4 board trace and 90-cm cable after setting the pre-emphasis boosting gain for 2.16 dB. The core area of the test chip is 0.066 mm2 and its power efficiency is 2.36 pJ/bit.

    摘要 III Abstract IV 誌謝 V Table of Contents VI List of Tables IX List of Figures X Chapter 1 Introduction 1 1.1 Introduction and Motivation 1 1.2 Thesis Organization 4 Chapter 2 Background Knowledge of Transmitters 6 2.1 Signal Coding Types 6 2.2 Basic Transmitter Circuits 8 2.2.1 Serializer Architectures 9 2.2.2 Basic Transmitter Driver Circuits with impedance matching 11 2.3 Pre-emphasis Method 12 2.3.1 Overview for Equalization 12 2.3.2 Feed-forward Equalizer 15 2.3.3 Traditional Transmitter Drivers with Impedance Matching and Pre-emphasis Techniques 21 2.4 Drivers of High Swing Voltage-Mode Transmitters 25 2.4.1 Traditional impedance matching techniques of SST drivers 26 2.4.2 A T-coil-Enhanced 8.5 Gb/s High-Swing Source-Series-Terminated Transmitter in 65 nm Bulk CMOS 28 2.4.3 A 32 mW 7.4 Gb/s Protocol-Agile Source-Series-Terminated Transmitter in 45 nm CMOS SOI 29 2.4.4 Fully Digital Transmit Equalizer With Dynamic Impedance Modulation 31 2.4.5 A 28-Gb/s Source-Series-Terminated TX in 32nm CMOS SOI 33 Chapter 3 A Low Power Duobinary Voltage-Mode Transmitter 35 3.1 Brief Introduction 35 3.2 Transmitter Architecture Consideration 36 3.2.1 Signal Coding Consideration 36 3.2.2 Typical Architecture Comparison 37 3.2.3 Impedance Matching Scheme 38 3.3 Proposed Transmitter 39 3.3.1 Output Driver 39 3.3.2 Pre-emphasis Method 40 3.4 Circuit Implementation 43 3.4.1 Overall Architecture 43 3.4.2 Divider Circuit 45 3.4.3 PRBS15 47 3.4.4 Serializer 48 3.4.5 Duobinary Control Signal Detection Circuit 49 3.5 Layout and Floor Plan 52 Chapter 4 Simulation and Measurement Results 55 4.1 Simulation Results 55 4.2 Die Micrograph and Measurement Setup 68 4.3 Measurement Results 71 Chapter 5 Conclusions and Future Works 78 5.1 Conclusions 78 5.2 Future Work 79 Bibliography 83

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