由於現代IC設計複雜度提升，晶片所需之測試資料量和測試時間也隨之飛快地成長。測試壓縮技術現已被廣為運用在工業上以降低測試所需成本。在這篇論文中，我們提出了一個簡單但有效率且只需極低額外面積成本的測試壓縮技術。我們發展出一套有效率的演算法來決定測試壓縮器之中不同測試工作階段的接線設定和相對應的測試向量。和之前的研究相比，這些演算法能用較低的中央處理器執行時間達到較高的測試壓縮比和較低的測試執行時間。在IWLS’05標準電路的實驗當中，我們平均可以增加17.33%的測試壓縮率、減少12.04%的測試執行時間和減少65.55%的中央處理器執行時間，且只需微量的額外面積負擔。

Test time and test data volume required to test modern integrated circuits grow rapidly with circuit complexity. Test compression is now widely used in industry to reduce test cost. In this thesis, a simple yet highly efficient test data compression technique with small area overhead is presented. Efficient algorithms are developed to determine configurations of the test decompressor and corresponding test patterns in multiple test sessions. These algorithms result in higher test compression ratio and lower test application time with less CPU runtime compared to the latest previous work. Experimental results on IWLS’05 benchmark circuits show that on average we can increase the compression factor by 17.33%, decrease the test application time by 12.04% and cut down the CPU time by 65.55%, with only slight increase of area overhead.

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