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研究生： 黃啟睿
Huang, Chi-Ray
論文名稱： 具有高能量效率與高可靠度之近臨界電壓靜態隨機存取記憶體
Highly Energy-Efficient and Reliable Near-Threshold SRAM
指導教授： 邱瀝毅
Chiou, Lih-Yih
學位類別： 博士
Doctor
系所名稱： 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年： 2021
畢業學年度： 109
語文別： 英文
論文頁數： 118
中文關鍵詞： 靜態隨機存取記憶體 、低功率 、低電壓 、次臨界電壓操作 、製程變異
外文關鍵詞： SRAM, Process Variation, Low Power, Low Voltage
相關次數： 點閱：78  下載：0 
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    • 無論是手持式或是微小化的電子產品，其對於長時間使用的需求與日俱增，催生出低功耗數位電路與系統的蓬勃發展。在數位系統中，靜態隨機存取記憶體影響了系統不管是動態功率消耗、靜態漏電流、運算效能、面積、甚至是良率。因此對於低功耗的數位系統而言，靜態隨機存取記憶體的設計便至關重要。為了降低動態與靜態功耗，調降操作電壓是一個有效的設計方法。然而，低電壓靜態隨機存取記憶體設計面臨來自製程變異的挑戰，其帶來的影響將導致記憶體的穩定性與良率降低。為了能夠讓靜態隨機存取記憶體在低電壓下正確地操作，輔助電路與高穩定性的記憶體單元為兩大設計主軸。本文因此以這兩大主軸為基礎，深入探討與分析低電壓，尤其是調降電壓至近臨界電壓區域的操作所帶來的影響與挑戰，並提出克服此影響所需要的相關設計技術。其研發重點摘要如下。首先，本文提出一具有選擇性偏壓能力的寫入輔助電路以及寫入能力偵測電路，解決傳統寫入輔助電路具有較大功耗付出的缺點。其次，本文更提出一低功耗單端位元線的記憶體單元，其不需要任何形式的輔助電路便能在低電壓下提供高穩定性的操作。本文另探討位元線漏電流對於單端讀取能力的影響，並提出能同時降低漏電流與讀取功耗的讀取阜以及相關控制技術。除了靜態隨機存取記憶體的動態功耗之外，本文提出自我資料保持電壓調節技術，來降低靜態隨機存取記憶體處於睡眠模式時的漏電流功耗，取代傳統電壓調降至固定式的最差情況設計。最後，本文亦提出具有廣訊號電壓轉換能力以及低靜態功耗的介面電壓準位轉換器，提供低電壓靜態隨機存取記憶體與其他不同電壓電路的溝通能力。以上所提出的新式電路設計技術，皆經過嚴謹的模擬以及實體晶片驗證，證明其低電壓的正確性與低功耗應用的可行性。

    The long-term operation requirements of devices with small dimensions have driven the development of low-power circuits and systems. Static random-access memories (SRAMs) substantially contribute to the dynamic energy, leakage power, system performance, and yield of integrated digital systems. To achieve high energy efficiency, scaling down the supply voltage is effective for digital systems on a chip (SoCs). Unfortunately, the exacerbated Vth shift with reduced VDD results in a diminished strength ratio of the conventional 6T SRAM cell and yields unstable operation, limiting the minimum achievable operating voltage for SRAMs. Researches related to peripheral assist circuits used to enlarge the strength ratio and different bit-cell structures have been developed to push the SRAM VDDmin reduction. This dissertation discusses the research and developments of the circuit techniques to enable low voltage and low power SRAM designs. The crucial achievements are organized as follows. First, an energy-efficient write assist circuit and write margin tracking method are proposed for saving assist overhead by conditionally activating the assist circuits. Second, a low-power single-BL 8T bit-cell structure that has high cell stability is proposed. This cell structure can operate down to the near-threshold region without the use of peripheral assist circuits. Third, the challenges of low energy and reliable single-ended read are investigated, and a dedicated read port with data-independent bitline leakage is proposed to reduce redundant read while improving sensing margin. In addition to the power reduction for active mode, a PVT-aware self VDD regulating scheme is proposed to maximize leakage saving for standby mode. Finally, a wide range level shifter from sub-to-super-threshold voltage is also designed to help the low voltage SRAM communicating to blocks with different supply voltages. Above mentioned techniques are verified with nanometer process technology, involving simulations and measurements.

    摘要 I Abstract III 誌謝 V Table of Contents VI List of Figure IX List of Table XIII List of Abbreviation XIV Chapter 1 Introduction 1 1.1 Low Power Microcontroller Application and Design Development 1 1.2 Low Voltage SRAM Design Challenges 4 1.2.1 Read Stability 4 1.2.2 Write Ability 7 1.2.3 Half-Select Stability 9 1.2.4 Read Sensing Margin 12 1.2.5 Data Retention Voltage 13 1.3 Dissertation Organization 14 Chapter 2 Conditional Biasing Write Assist and Write Margin Tracking 16 2.1 Background of Write Operation 16 2.1.1 Write Failure Mechanism 16 2.1.2 Write Margin Definition 17 2.2 Conventional Low Energy Write Assist Circuits 19 2.3 Variation-Aware Write Assist Techniques 20 2.3.1 Motivation of Variation-Aware Assistance 20 2.3.2 Related Works 21 2.4 Proposed Conditional Biasing Write Assist Circuit 23 2.4.1 Circuit Structure of Conditional Biasing Write Assist 24 2.4.2 Operations of Conditional Biasing Write Assist 26 2.5 Write Assist Characteristics 32 2.5.1 Area Overhead 34 2.5.2 Write Failure Rate 34 2.5.3 Write Time 35 2.5.4 Write Energy 36 2.6 Test Chip and Measurement Results 39 2.7 Summary 40 Chapter 3 Single-BL 8T Bit-cell with Asynchronous Dual Wordline Control 41 3.1 Previous Solutions for Half-Select Disturb Issue 41 3.2 Proposed Single-BL 8T Bit-cell 43 3.2.1 Cell Structure 43 3.2.2 Asynchronous Dual Wordline Control 45 3.3 Cell Performance Analysis 49 3.3.1 Hold, Read, and Half-Select Stability 51 3.3.2 Write Ability and Write Time 54 3.3.3 Technology Scaling 57 3.4 Test Chip and Measurement Results 58 3.5 Summary 61 Chapter 4 Low Read Energy and Reliable Read Sensing Design 62 4.1 Conventional Designs for Read Energy Reduction and Read Sensing Margin Improvements 62 4.2 Proposed Low Read Energy and Reliable Read Port 67 4.2.1 Cell Structure 67 4.2.2 Operating Principle 68 4.3 Experiment Results 76 4.3.1 Cell Area 76 4.3.2 Read Sensing Margin 78 4.3.3 Power and Performance 80 4.4 Summary 82 Chapter 5 PVT-Aware Self Data Retention Voltage Scaling Scheme 83 5.1 VDD-Scaling Solutions for Ultra-Low Standby Power SRAM 83 5.2 System Architecture of PVT-Aware Self-DRV Scaling Scheme 87 5.2.1 System Implementation and Operation 87 5.2.2 Circuit Design of Key Blocks 89 5.3 Measurement Results and Discussion 91 5.4 Summary 94 Chapter 6 Wide Conversion Range Cross-Coupled-Based Level Shifter 95 6.1 Design Challenges of Sub-Threshold Level Conversion 95 6.2 Previous Sub-Threshold Level Conversion 96 6.3 Proposed Circuit Structure 98 6.4 Experiment Results 100 6.5 Summary 103 Chapter 7 Conclusion and Future Work 104 7.1 Conclusion 104 7.2 Future Work 105 Reference 107 Appendix: Static and Dynamic Noise Margin 116

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