本論文主旨在於實現H.264影像壓縮標準編解碼器中的去區塊效應濾波器。 我們提出了一個可支援圖框式與圖場式圖片可調性編碼，以及圖框式與圖場式巨集方塊可調性編碼的去區波塊效應濾波器架構，並盡可能使得資料流在各個編碼模式中簡單化，如此不僅可以使控制信號簡化，也可以一套資料流來完成我們所要支援的各種編碼模式。
在設計架構前我們會先以不同單位大小的區塊為處理的單位，並搭配不同的資料流，和濾波器處理元件的平行度展開設計空間，儘可能提高濾波器處理元件的使用率和資料的重新使用率以減少相同資料重覆存取的次數。
在所展開的設計空間中，時脈、平均頻寬、尖峰頻寬、匯流排寛度、和內部記憶體的大小都將同時被比較用來決定我們的架構設計所取捨的要素。此發表的架構比一般只支援正常模式的去波塊效應濾波器多了更高的規格支援和高影像頻率並且提高了圖像的解析度。
此架構利用TSMC 0.18μm的製程技術合成，其合成的結果顯示所提出的去區塊濾波器架構在工作時脈為108MHz的情況下，每秒可處理六十張解析度為1920×1088的影像。

This thesis focuses on the implementation of the de-blocking filter of H.264 video compression codec. The dataflow and corresponding architecture are developed to support the Picture Adaptive Field and Frame (PAFF) coding mode and MacroBlock Adaptive Field and Frame coding (MBAFF) modes. An attempt is also made to simplify the data flow not only to clarify the control flow, but also to complete all coding modes supported in a data flow.
Prior to the architecture is designed, the processing unit is processed using different granularities. Data flows with the different granularities and parellel processing of processing element (PE) are managed to explore the design space.
Increasing the utilization of filtering PE and data reuse can reduce data access time. Exploring the design space, involves determining the trade-off in architectural design by comparing the operating frequency, average bandwidth, bus bitwidth, and internal buffer size. The proposed architecture supports a main profile, high frame rate and improved picture resolution.
The proposed architecture is synthesized with a TSMC 0.18μm technology cell library, demonstrating that the de-blocking filter being able to process the filtering operations at 60 frames per second with a resolution of 1920×1088 real time at a frequency of 108MHz.

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