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研究生：	黃志豪 Huang, Chih-Haur
論文名稱：	高速管線式類比數位轉換器之設計及診斷技術 Design and Diagnosis of High Speed Pipelined A/D Converters
指導教授：	李昆忠 Lee, Kuen-Jong
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 電機工程學系 Department of Electrical Engineering
論文出版年：	2004
畢業學年度：	92
語文別：	英文
論文頁數：	165
中文關鍵詞：	管線式類比數位轉換器
外文關鍵詞：	Pipelined A/D Converters
相關次數：	點閱：85 下載：3
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　　管線式類比數位轉換器擁有高速的特性可以廣泛的應用在寬頻通訊及視訊系統。隨著系統單晶片的潮流，類比及數位電路整合在單一顆晶片中，其帶給類比及混合訊號積體電路設計許多挑戰，譬如說，低電壓設計，低訊號雜訊比，短通道長度影響及可測試性設計。由於這些趨勢，我們需要資料轉換器擁有以下特性: 高轉換速度，高解析度，低晶片面積及低功率消耗。
　　本論文包含三個類比/數位轉換器設計及診斷之研究成果。在第一個研究當中，我們採用了台積電0.25微米互補式金氧半製程去設計及研製了一個10位元每秒取樣91百萬次的管線式類比數位轉換器。此晶片可應用於液晶顯示器控制晶片及高畫質數位電視，且其面積與操作電壓分別僅有2.173 及2.5伏特。模擬結果為在每秒91百萬次的操作頻率下可有60.4dB的訊號雜訊失真比及73dB無雜訊影響動態範圍，然而實際晶片量測結果則顯示在每秒40百萬次的操作頻率下只有41dB的訊號雜訊失真比及45dB無雜訊影響動態範圍。
　　在設計高解析度管線式類比數位轉換器中，最大的困難點在於製程偏移所造成的電容不匹配問題，此問題將會導致非線性及諧波失真，進而限制類比數位轉換器的解析度。所以在第二個研究中，我們提出了一個新型的多重相位電容分離回授交換技術來克服因電容不匹配所造成的誤差。實驗的結果說明我們提出的技術擁有低微分型與積分型非線性誤差，及高訊號雜訊失真比與無雜訊影響動態範圍。在這裡，我們採用此技術設計並研製了一個12位元每秒取樣40百萬次的管線式類比數位轉換器。此晶片可應用於無線通訊，其操作電壓為2.5伏特，且整個晶片及多重相位電容分離回授交換技術之面積分別僅有3.916 及0.0765 。模擬結果為在每秒40百萬次的操作頻率下可有71dB的訊號雜訊失真比及80dB無雜訊影響動態範圍，而實際晶片量測結果則顯示在每秒35百萬次的操作頻率下可有61.7dB的訊號雜訊失真比及65dB無雜訊影響動態範圍。此研究之相關成果發表於2004年IEEE亞太積體電路與系統設計會議接受為正式論文。
　　在第三個研究中，我們提出了一個新的管線式類比數位轉換器之低成本診斷方法，此方法運用了以下三種技術: (1)分時多工，(2)掃瞄式測試，(3)電壓控制震盪器量測。其中第三種技術是用來測試取樣保持電路及乘法式數位類比轉換器輸出之精確性，其具有對製程偏移及雜訊所造成之錯誤不敏感的特性。由於此診斷策略僅需低複雜度及低晶片面積之內建式自我測試電路，所以我們所提出的方法具有低成本且低功率消耗的特性。我們以十二位元類比數位轉換器為例，在TSMC 0.25μm CMOS 1P5M製程下針對上述測試策略架構進行設計及模擬，經由實驗結果可驗証本研究所提出的測試策略具有低成本及低晶片面積之診斷特性。此研究之相關成果發表於2004年IEEE亞洲測試會議選為正式論文。

　　Pipelined A/D Converters (ADCs) have intrinsic high-speed characteristics and are commonly used in wideband communication and video systems. With the trends of SOC, both analog and digital circuits are implemented on the same silicon, which will bring many challenges for analog and mixed-signal design, such as lower supply voltages, lower SNR, short channel effects and design for testability. Due to theses trends, there is an urgent necessity to design data converters with high conversion rate, high resolution, low area and low power consumption.
　　In this thesis, we have accomplished three research results on the design and diagnosis of ADCs. In the first work, a 10-bit 91MS/s pipelined A/D converter has been designed and implemented with the TSMC 0.25um CMOS 1P5M process. The applications of this ADC are focused on the high resolution LCD controller and the HDTV. The chip area and supply voltage of the chip are only 2.173 and 2.5V. The simulation results show that the SNDR and SFDR are 60.4dB and 73dB at 91 MHz sampling frequency. However, the measured results show that the SNDR and SFDR are only 41dB and 45dB at 40 MHz sampling frequency, respectively.
　　The main limitation of high-resolution pipelined ADCs is capacitor mismatch, which will cause non-linearity and harmonic distortion and thus often limit the resolution of ADCs. So in the second work, we propose a new technique, the Multiple-Phase Capacitor-Splitting Feedback Interchange (MP-CSFI) technique, to overcome this problem. The experimental results show that the proposed scheme has the advantages of low DNL, low INL, high SNDR and SFDR. A 12-bit 40MS/s pipelined ADC with the MP-CSFI technique has been designed and fabricated. The supply voltage is 2.5V, and chip areas of the 12-bit ADC and MP-CSFI technique are only 3.916 and 0.0765 , respectively. The simulation results show that the SNDR and SFDR are 71dB and 80dB at 40 MHz sampling frequency. The measured results show that the SNDR and SFDR are 61.7dB and 65dB at 35 MHz sampling frequency, respectively. This work has been accepted by the 2004 IEEE Asia-Pacific Conference on Circuits and Systems (APCCAS'04) as a full paper.
　　In the third work, we propose a novel low-cost diagnosis methodology for pipelined A/D converters. The methodology manipulates three techniques in the diagnosis process: (1) time-division-multiplexing (TDM), (2) scan based testing, and (3) VCO based measurement. The last technique is developed to diagnose the most critical mixed-signal functional blocks, e.g. SHA and MDAC in the pipelined ADC. It provides a great capability to distinguish signals with very small voltage difference. Also it is insensitive to process variations and immune to noise induced errors. Furthermore, the diagnosis methodology is power- and area- efficient because it only needs low-complexity and low-area BIST circuits to accomplish the full diagnosis process. A 12-bit pipelined A/D converter with the proposed diagnosis scheme is designed and simulated using the TSMC 0.25um 1P5M technology to demonstrate the effectiveness of the proposed methodology. This work has been accepted by the 2004 IEEE Asian Test Symposium (ATS'04).

TABLE OF CONTENTS

Acknowledgment……………………………………………………………I
Abstract………………………………………………….………..….……..II
Table of Contents………………………………………………...……….VII
List of Tables…………………………………………………..…………XIII
List of Figures……………………………………….…………….………XV
.
Chapter 1 Introduction	1
1 Motivation	1
2 Applications of Analog-to-Digital Converters	3
3 Organization of Thesis	7

Chapter 2 Fundamentals of Pipelined A/D Converters	9
1 Introduction	9
2 ADC Performance Metrics	9
2.1 Resolution	10
2.2 Signal to Noise Ratio (SNR)	10
2.3 Signal to Noise + Distortion Ratio (SNDR)	12
2.4 Dynamic Range (DR)	12
2.5 Spurious Free Dynamic Range (SFDR)	13
2.6 Nonlinearity	13
3 Review of ADC Architectures	14
3.1 Flash ADC	14
3.2 Two-Step ADC	15
3.3 Folding and Interpolating ADC	16
3.4 Successive Approximation ADC	17
3.5 Sigma-Delta ADC	19
3.6 Pipelined ADC	22
3.7 Comparison among ADC Architectures	23
4 Key Building Blocks of Pipelined ADC	24
5 Digital Error Correction Technique	27
6 Error Sources in Pipelined Stage	29
6.1 Thermal Noise	29
6.2 Comparator Offsets	30
6.3 Non-ideal DAC Reference Levels	31
6.4 Stage Gain Error	32
7 Pipelined Stage Accuracy Requirements	34
8 Summary	37

Chapter 3	The Design and Implementation of 10-bit 91MS/s Pipelined A/D Converter	39 
1 Previous Work about High-Speed Pipelined ADCs	39
1.1 Introduction	39
1.2 Parallel Pipelined ADC Technique	40
1.2.1 Timing Mismatch	42
1.2.2 Channel Offset	43
1.2.3 Channel Gain Mismatch	43
1.3 Selecting Stage Resolution	44
1.4 Summary	48
2 The Design and Implementation of 1.5 bit/stage Pipelined A/D Converter	48
2.1 Introduction	48
2.2 1.5 bit/stage System Architecture of Pipelined ADC	49
2.2.1 Operational Principle	49
2.2.2 Behavior Model of Pipelined ADC	52
2.2.3 Non-ideality Considerations	54
2.2.4 Summary	57
2.3 Circuit Design and Implementation	57
2.3.1 Sample and Hold Amplifier	57
2.3.2 Sub-Analog-to-Digital Converter	59
2.3.3 Multiplying Digital-to-Analog Converter	60
2.3.4 Operational Amplifier	61
2.3.5 Comparator	64
2.3.6 Digital Error Correction	65
2.3.7 Clock Generator	65
2.3.8 Chip Simulations	66
2.3.9 Layout and Floor Plan	71
2.3.10 Summary	72
3 Test Setup and Experimental Results	72
3.1 The Package and Pin Configuration	72
3.2 Test Setup	74
3.3 Experimental Results	76
3.4 Summary	79
4 Conclusions	80

Chapter 4	The Design and Implementation of 12-bit 40MS/s Pipelined A/D Converter using MP-CSFI Technique	81 
1 Previous Work about High-Speed and High- Resolution Pipelined ADCs	81
1.1 Introduction	81
1.2 Trimming Technique for Pipelined ADCs	82
1.3 Capacitor Error-Averaging Technique for Pipelined ADCs	83
1.4 Digital Calibration Technique for Pipelined ADCs	85
1.5 Commutated Feedback-Capacitor Switching (CFCS) Technique for Pipelined ADCs	88
1.6 Summary	91
2 The Design and Implementation of MP-CSFI Pipelined A/D Converter	92
2.1 Introduction	92
2.2 Proposed Multiple-Phase Capacitor-Splitting Feedback Interchange (MP-CSFI) Technique	93
2.3 MP-CSFI System Architecture of Pipelined ADC	96
2.3.1 Operational Principle	96
2.3.2 Behavior Model of MP-CSFI Pipelined ADC	98
2.3.3 Simulation Results and Comparisons	99
2.3.4 Summary	105
2.4 Circuit Design and Implementation	106
2.4.1 Sample and Hold Amplifier	106
2.4.2 Dynamic Comparator	107
2.4.3 Operational Amplifier	109
2.4.4 Chip Simulations	110
2.4.5 Layout and Floor Plan	114
2.4.6 Summary	115
3 Test Setup and Experimental Results	115
3.1 The Package and Pin Configuration	115
3.2 Test Setup	117
3.3 Experimental Results	119
3.4 Summary	123
4 Conclusions	123

Chapter 5	A Low-Cost Diagnosis Methodology For Pipelined A/D Converters	125 
1 Background and Previous Work	125
1.1 Introduction	125
1.2 Histogram Test Technique	126
1.3 BIST for Digital-to-Analog Converters and Analog-to- Digital Converters	126
1.4 MDAC and Stage Testing for Pipelined ADCs	129
1.5 Frequency Domain Testing	131
1.6 Summary	132
2 A Low-Cost Diagnosis Scheme	132
2.1 Introduction	132
2.2 Architecture of Pipelined ADCs	133
2.3 Low-Power and Low-Area VCO Based Measurement Scheme	134
2.3.1 VCO Based Measurement Method	134
2.3.2 Linear VCO	136
2.3.3 Summary	137
2.4 Diagnosis Principle	137
2.4.1 Diagnosis Flow and Techniques	137
2.4.2 Diagnosis Architecture	145
2.4.3 Summary	146
3 Simulation and Experimental Results	146
3.1 Linear VCO	146
3.2 VCO Based Measurement Scheme	147
3.2.1 SHA Test	147
3.2.2 Stage Test	149
3.3 Layout Floor Plan	151
3.4 Summary	152
4 Conclusions	152

Chapter 6	Conclusions and Future Work	153
1 Design Summary	153
1.1 Conclusions	153
1.2 Future Work	154
2 Testing Summary	155
2.1 Conclusions	155
2.2 Future Work	156

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校內：2008-07-13公開
校外：2010-07-13公開

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