近年來人工智慧成為最熱門的主題，且其中的機器學習更是現今成長最快速的領域之一，各種不同的演算法誕生也進入了許多領域中，如市場預測、醫療輔助、圖像及語音辨識皆被廣泛探討。而若提到機器學習就必須提到最早開始發展且最主流的神經網路，其中又以圖片辨識的卷積神經網路發展最為成熟且最受歡迎，卷積神經網路藉由輸入的圖片以及神經網路中的權重(Weight)對圖片進行辨識也被稱為推論(Inference)並將誤差回傳至伺服器端進行訓練(Training)，隨著卷積神經網路的發展，設計具有高能量效率且同時支援推論以及晶片內訓練的加速器的必要性與日俱增。
本論文中不僅提出一針對卷積神經網路之加速器架構，並且我們採用了高能量效益(Energy Efficiency)的記憶體內運算作為加速器中的主要運算單元，且同步支援神經網路推論以及晶片內訓練，透過晶片內訓練機制加強使用者資料之隱私安全性。此加速器以電子系統層級建置，能有彈性地提供設計者於加速器內進行架構探勘與效能評估。

Nowadays, Artificial Intelligence (AI) has become a popular topic and machine learning is one of the fastest growing fields. Various kinds of algorithms are applied in many different applications such as market prediction, medical assistance as well as image or speech recognition. In machine learning, the earliest and mainstream algorithm is neural network. Moreover, convolutional neural network (CNN) widely applied in the image recognition field is more popular than other networks. CNN implement image prediction as known as inference by input images and weights in CNN model then upload prediction error to server for CNN training. As the CNN development evolves, it is becoming essential to design a high energy efficient hardware that can support inference and on-chip training at the same time.

In this work, we not only proposed an accelerator architecture focusing on CNN applications, but also adopt computing-in-memory (CIM) as the main processing unit of the accelerator. When personal data can be processed by on-chip training mechanism, users’ data privacy can be protected. The proposed accelerator is built at electronic system level and capable of making designers to explore accelerator architecture and evaluate performance.

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