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研究生：	劉政威 Liu, Zheng-Wei
論文名稱：	使用自動調整寫入技術以提升寫入穩定度之鄰近臨界電壓的靜態隨機存取記憶體 Enhanced Write-Stability using a Self-Bias-Write Technique for Near-threshold Voltage SRAMs
指導教授：	邱瀝毅 Chiou, Lih-Yih
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 電機工程學系 Department of Electrical Engineering
論文出版年：	2017
畢業學年度：	105
語文別：	英文
論文頁數：	70
中文關鍵詞：	靜態隨機存取記憶體、低功率、低功率、寫入輔助技術、額外面積
外文關鍵詞：	SRAM, low voltage, low power, write assist technique, area overhead
相關次數：	點閱：89 下載：1
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近年來隨著科技蓬勃發展及環保意識抬頭，大部分產品和發展趨勢大部分都朝向低功率消耗的發展，同時也希望能夠達到輕薄短小的特性，目的就是為了延長小尺寸的產品之電池的使用壽命，而在整體系統中以靜態隨機存取記憶體的能量消耗為主宰，因此，為了降低靜態隨機存取記憶體的功率消耗而陸續衍生出許多低功率消耗之研究，其中以降低操作電壓為常用且有效的方式之一，然而降低操作電壓雖然可以大幅降低功率消耗，但是卻遭受嚴重的製程變異影響。尤其當電路操作在近臨界電壓或是次臨界電壓以下時，電晶體的電流將跟臨界電壓的變異成指數形式的關係，進而影響到靜態隨機存取記憶體操作功能的正確性以及功率消耗等等，造成靜態隨機存取記憶體中的讀取雜訊邊界及寫入雜訊邊界降低，最差的情況則會導致讀取或寫入發生錯誤，因此，針對上述情況已經發展出許多讀取或寫入輔助技術應用於低電壓操作的設計中，而在這篇論文中，將會針對寫入部分提出寫入輔助技術，目的是解決低電壓操作時寫入能力不足的情況，使其可操作於近臨界電壓，同時考量額外面積消耗，找出較佳的解達到低功率消耗且小尺寸的設計。而最後我們以40奈米製程下線並做佈局後模擬驗證。

In recent years, for the promising growth of technology and eco-friendly sense, most of the products and development are working toward low-power consumption while maintaining small size. The purpose is to provide longer battery’s lifetime of product as the volume decrease. Static random access memory (SRAM) is one of major sources of power consumption in the SOC, as a result, many researches have investigated low-power consumption techniques. Among them, scaling supply voltage is a common and effective way. Although the power consumption can be greatly reduced, but it is affected significantly by process variations. Especially, when the circuit is operated at near-threshold voltage or sub-threshold voltage, the transistor's current is exponentially increased near the threshold voltage. The consequence is that the process variation affects the correctness of SRAM's functionality and power consumption due to reduction of read/write noise margin, and read/write error occurs in the worst case. In this thesis, we focus on how to solve the insufficiency of write ability for low-voltage operation, so that the memory can be operated at the near-threshold voltage. In the meanwhile, we also find the optimal design by considering tradeoffs between power consumption and area. Finally, a test chip is fabricated using 40nm process to demonstrate the proposed write assist technique.

摘 要......i
Abstract......ii
致 謝......iii
Contents......iv
List of Tables......vi
List of Figures......vii
Chapter 1  Introduction......1
1   Background......1
1.1   Preliminary......1
1.2   Write operation of SRAM cell at the low voltage......2
1.3   Write Noise Margin (WNM)......3
1.4   Stability of Half-Selected cells......6
2   Motivation......9
3   Contributions......9
4   Thesis organization......10
Chapter 2  Recently Published Write Assist Techniques......11
1   Boost Word-Line......11
2   Negative Bit-Line......14
3   Gating power supply......16
4   Gating ground......18
5   Summary......20
5.1   Write noise margin for different write assist techniques......20
5.2   Stability of half-selected cells......22
5.3   Summarize these write assist techniques......23
Chapter 3  Proposed write assist technique......25
1   Proposed write assist technique and design concept......25
1.1   Write operating flow of proposed write assist design......26
1.2   Half-selected cells stability issue......28
2   Architecture of ultra-low operating voltage SRAM......33
3   Overall Architecture......35
Chapter 4  Test Chip Implementation......37
1   Chip planning......37
1.1   Operating flow of overall architecture......38
1.2   Placement and layout consideration......39
2   BIST design......44
Chapter 5  Simulation Results......47
1   Scaling cell number of virtual ground......47
2   Write noise margin for write assist techniques......50
3   The stability of the column half-selected cells for write assist techniques......52
4   Minimum operating voltage & power consumption for write assist techniques......53
5   Area overhead for write assist techniques......54
6   Post-layout simulation results of function for the proposed write assist design......56
7   Comparison......57
Chapter 6  Chip Measurement......59
1   Measurement flow......61
2   Test results......61
Chapter 7  Conclusions and Future Works......63
1   Conclusions......63
2   Future works......64
References......65
個人簡歷......69

                                    

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校內：2022-08-31公開
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