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研究生： 陳威志
Chen, Wei-Chih
論文名稱： 增加回授時間及不需額外主動加法器之低失真三角積分調變器設計
Design of a Low-Distortion Sigma-Delta Modulator with Relaxed Feedback Path Timing without Extra Active Adder
指導教授： 劉濱達
Liu, Bin-Da
學位類別： 碩士
Master
系所名稱： 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年： 2011
畢業學年度： 99
語文別： 英文
論文頁數： 79
中文關鍵詞： 低失真三角積分調變器 、增加反授時間技術 、資料加權平均演算法
外文關鍵詞： Low-distortion sigma-delta modulator, feedback timing relaxed technique, data weighted averaging algorism circuit
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    • 本論文提出適用於無線通訊系統寬頻三角積分調變器，其設計目標是達到高解析度以及低功率消耗。傳統低失真三角調變器的特色是只需要處理量化誤差，因此能夠降低積分器的規格以節省功率消耗。然而，此架構在運用於高速的設備時，回授的數位訊號所需要的時間較長，但僅能在時脈的相位間完成所有數位電路處理，因此這是低失真三角調變器在速度上的瓶頸。此外低失真三角調變器有許多前饋路徑，處理這些路徑的訊號需要一個額外的加法器，而增加功率消耗。在提出的新架構當中，解決了上述兩個議題。首先，推導出能增加回授時間的新型三階的三角積分調變器架構，解決速度上的問題；再來利用前饋的電容性輸入技術，在最後一級積分器即能完成加法器的功能，因而消除額外的加法器。研究的新型低失真三角調變器不但能以更節省功率的方式達到同樣解析度，更不需要使用額外的加法器，並且解決回授路徑的時間問題。所設計的三角積分調變器使用三階低失真單迴路、四位元量化器，此外於回授路徑使用資料加權平均演算法，以降低電容不匹配。
    此電路設計的製程進行模擬使用0.18微米，1層多晶矽6層金屬線製程設計，1.8伏特供應電壓。從模擬結果得知此當此調變器操作於1百萬赫茲訊號頻寬、24倍超取樣率時，訊噪比為80.3 dB，並消耗功率40.2毫瓦。

    In this thesis, the proposed sigma-delta modulator is suitable for the use in wireless communication system. High resolution and low power consumption are goals for this application. The important characteristic of low-distortion sigma-delta modulator is that it can reduce power consumption because integrators only deal with the quantization noise. But this structure is also following by some disadvantages. The speed bottleneck of low-distortion sigma-delta modulator is that the critical delay in feedback path is hard to achieve in non-overlapping time interval for high speed application. Besides, an extra adder is required to sum up the input feed-forward paths in front of the quantizer. This adder consumes extra power. The proposed architecture solves timing issue without an extra adder. First, the third order of sigma-delta modulator is derived to relax feedback timing. Moreover, in order to eliminate an extra adder, capacitive input feed-forward technology is used to add the input feed-forward signals in front of the last integrator. In sum, this work is used in third-order, 4-bit quantizer with DWA algorism circuit.

    The proposed low-distortion third-order sigma-delta modulator is simulated in a 0.18-μm 1P6M 1.8-V CMOS technology. From the simulation results, a 80.3-dB SNR is achieved with 40.2-mW total power consumption under 24-X oversampling ratio at 100 MHz sampling frequency.

    Abstract iii Acknowledgement v List of Tables ix List of Figures x Chapter 1 Introduction 1 1.1 Motivation and Background 1 1.2 Organization of the Thesis 2 Chapter 2 Fundamentals of Sigma-Delta Converter 4 2.1 Introduction of sigma-delta modulator 4 2.2 Introduction of digital filter 8 Chapter 3 Proposed Novel Sigma-Delta Modulation Structure 11 3.1 Low-Distortion ΣΔ ADC 11 3.1.1 Conventional low-distortion modulator 12 3.1.2 Improved low-distortion modulator 15 3.2 ΔΣ modulator with relaxed feedback timing 22 3.2.1 ΔΣ modulator with relaxed feedback timing 23 3.3 Proposed novel low-distortion sigma-delta modulator 25 3.3.1 The proposed architecture 26 3.3.2 Timing diagram 31 3.3.3 Matlab Simulation 32 3.4 Summary 37 Chapter 4 Implementation in Circuit Level 38 4.1 Loop filter Design 38 4.1.1 Specification of the sigma-delta modulator 38 4.1.2 Integrator 40 4.1.3 op-amp 49 4.2 Quantizer design 52 4.2.1 Asynchronous binary-search 52 4.2.2 Comparator 53 4.2.3 Clock logic 54 4.2.4 Reference ladder 56 4.2.5 Thermometer decoder 57 4.2.6 Summary 59 4.3 Data weighted averaging and digital-to-analog circuit design 60 4.3.1 Bubble correction 62 4.3.2 ROM encoder 62 4.3.3 Point generator 64 4.3.4 4-bit to 16-bit decoder 65 4.3.5 Barrel shifter 65 4.4 Clock generator 67 4.5 Experimental Results 69 Chapter 5 Conclusions and Future Work 73 5.1 Conclusions 73 5.2 Future Work 75 References 76

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