本論文實現一個14位元10GS/s之電流汲取式數位類比轉換器，並提出一突波補償技術解決非歸零式數位類比轉換器在輸出訊號發生變化時所產生之暫態非線性。藉由即時計算相鄰兩輸入碼之間的變化，並利用一輔助數位類比轉換器產生補償突波，可大幅降低高速運作時，碼相依突波對數位類比轉換器輸出信號線性度的影響。此外，為改善輸出電流源之間的匹配，本論文採用實驗室先前所提出之二元權重選取之動態匹配技術以及同心平行四邊形繞線法，改善電流源間的隨機與梯度不匹配所產生之非線性。最後，使用實驗室先前所提出的輸出阻抗補償技術，調整輸出點所並聯之電阻，可大幅減少單位電流源所需的輸出阻抗與所需成本，使得本論文所提出之數位類比轉換器在較低的操作電壓下依然保持良好的輸出信號線性。

此電流汲取式數位類比轉換器採用台積電 28奈米，1P10M互補金氧半導體製程，整個晶片主動面積約為0.1平方毫米。量測結果顯示，此類比數為轉換器可在10GS/s的操作速度下，可在奈奎氏頻寬內達成無雜散動態範圍數值高於64dB。此外與近年一流文獻相比，本作品之綜合性能指標堪稱世界最佳。

A 14-bit 10GS/s current-steering digital-to-analog converter (DAC) is realized to overcome three non-linearity sources in this thesis. Firstly, to reduce the switching transient non-linearity when the output signals of non-return-to-zero (NRZ) DAC toggling, a novel technique which named switching glitch compensation (SGC) is presented. By detecting the relationship between any two adjacent input codes, then, launching the compensation glitch with an assistant DAC, the transient non-linearity induced by code-dependent switching glitch could be greatly eliminated in high operation speed. Secondly, to overcome the gradient and random mismatch between current source arrays, the concentric parallelogram routing and the random-rotated-based selection techniques which proposed by our laboratory would be applied, respectively. Finally, the output impedance compensation (OIC) technique is adapted to remedy the output-voltage-dependent output current caused by finite output impedance and keeping great output signal linearity under low operation voltage.
This current-steering DAC use fabricated in TSMC 28nm 1P10M technology with 0.1mm2 active area. The measurement result shows that the DAC achieve the spurious free dynamic range (SFDR) > 64dB in full Nyquist bandwidth at 10GS/s with power consumption less than 180mW. And, comparing to state-of-the-art, this DAC has the best figure-of merit (FoM).

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