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研究生：	朱耿宏 Chu, Keng-Hong
論文名稱：	一個具自動校正位移功能及十個微微秒解析度之十位元混合式數位時間轉換器 A 10-bit Segmented Digital-to-Time Converter with 10ps-level Resolution and Automatic Offset Calibration
指導教授：	魏嘉玲 Wei, Chia-Ling
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 電機工程學系 Department of Electrical Engineering
論文出版年：	2014
畢業學年度：	102
語文別：	英文
論文頁數：	67
中文關鍵詞：	數位時間轉換器、混合式、位移量校正
外文關鍵詞：	Digital-to-Time Converter, Segmented, Offset Calibration
相關次數：	點閱：175 下載：3
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本論文提出一個具自動校正位移功能及十個微微秒解析度之十位元混合式數位時間轉換器‧不同於常見的延遲鎖定迴路以及相位鎖定迴路等功耗高的閉迴路式架構，本論文利用數位類比轉換器混合式切換模式 (二位元二進位切換模式加上八位元溫度計切換模式)的概念在數位時間轉換器上面，來減低製程變異對線性度的影響，以達到功耗較低的數位時間轉換器。另外，採用相對時間的架構以達到高解析度(10ps)，並加入一個校正位移誤差的電路，以消除相對時間架構的位移誤差量問題。
本電路所使用的製程為TSMC 1P6M 0.18µm混合訊號製程，解析度為10ps等級，最大工作時間為10n等級，總功率消耗為19mW，主要晶片面積為0.7mm2。

A 10-bit segmented digital-to-time converter with 10-ps-level resolution and automatic offset calibration is proposed. The segmented architecture (2-bit binary code +8-bit thermometer code) used in digital-to-analog converters (DAC) is adopted in the proposed digital-to-time converter (DTC) to reduce the impact of process variation on linearity. This method is different from conventional DTCs using delay-locked loops (DLL) or phase-locked loops (PLL), both of which have more power consumption. The proposed DTC uses the relative time generation to get high resolution, and the offset calibration circuit is implemented to calibrate the offset error inherent in the relative time generation.
The proposed DTC was fabricated by using the TSMC 0.18μm 1P6M mixed-signal process. The resolution of proposed is 10ps-level, and the operational range is 10ns-level. The total power consumption is 19mW. The core area is 0.7mm2.

Chapter 1	Introduction	1
1.1 Motivation	1
1.2 Organization	1
Chapter 2	Fundamentals of Digital-to-Time Converter	2
2.1 Introduction	2
2.2 DTC Performance Metrics	2
2.2.1 Resolution	2
2.2.2 Operational Range	3
2.2.3 Offset Error	3
2.2.4 Nonlinearity	4
(A). Differential Nonlinearity	4
(B). Integral Nonlinearity	5
2.3 Review of DTC architecture	5
2.3.1 Time Delay Generation	5
(A). Control the Reference Voltage	6
(B). Control the Charging Current	7
(C). Control the Load Capacitance	8
2.3.2 Architecture of DTC	9

Chapter 3	Analysis and Circuit Implement	15
3.1 Block Diagram	15
3.2 Analysis of Digital-to-Time Converter	16
3.2.1 Analysis of Controlling Method	17
(A). Current	17
(B). Capacitance	19
(C). Comparison	19
3.2.2 Switching Method	21
(A). Binary-Weighted Architecture	21
(B). Thermometer-Weighted Architecture	23
(C). Segmented-Weighted Architecture	24
(D). Comparison and Conclusion	24
3.3 Circuit Implement	27
3.3.1 Digital-to-Time Converter	27
(A).	Resolution of DTC	28
(B).	Current Source	29
(C).	Comparator	30
(i).	Specification	30
(ii).	Open-Loop Comparator	31
(iii).	Latch Comparator	32
(iv).	Cascade Comparator	33
3.3.2 Offset Calibration Circuit	34
(A).	Phase Detector	36
(B).	Pulse Generator	37
Chapter 4	Simulation Results and Layout Consideration	39
4.1 Simulation Results	39
4.1.1 Phase Detector	39
4.1.2 Preamplifier of Comparator	40
4.1.3 Digital-to-Time Converter	41
4.1.4 Offset Calibration Circuit	44
4.2 Layout	46
4.2.1 Layout Consideration	46
4.2.2 Bonding Diagram	48
Chapter 5	Measurement Results	49
5.1 Measurement Environment and Consideration	49
5.2 Measurement Results	52
5.2.1 10ps-level DTC	52
5.2.2 10ns-level DTC	58
Chapter 6	Conclusion and Future Work	63
Reference	65
                                    

[1] P. Y. Chen, J. S. Lai, and Y. J. Chen, “FPGA Vernier Digital-to-Time Converter with 1.58ps Resolution and 59.3Minutes Operation Range,” IEEE TCAS-I., vol. 57, no. 6, pp. 1134–1142, Jun. 2010.
[2] S. Katsu, T. Ueda, M. Kazumura, and G. Kano, “A GaAs programmable timer with 125ps delay-time resolution,” in Proc. IEEE ISSCC Dig., Feb. 1988, pp. 16–17.
[3] M. Suda, K. Yamamoto, T. Okayasu, S. Kantake, S. Sudou, and D.Watanabe, “CMOS high-speed, high-precision timing generator for 4.266-Gbps memory test system,” in Proc. IEEE ITC., Nov. 2005, pp.866.
[4] S. Alahdab, A. Mantyniemi, and J. Kostamovaara, “A 12-bit digital-to-time onverter (DTC) with sub-ps-level resolution using current DAC and differential switch for time-to-digital converter (TDC),” in Proc. IEEE International Instrumentation and Measurement Technology Conf. (I2MTC), May 2012, pp. 2668–2671.
[5] C. W. Branson, “Integrated pin electronics for a VLSI test system,” IEEE Trans. Ind. Electron., vol. 36, pp. 23–27, May 1989.
[6] T. I. Otsuji and N. Narumi, “A 3-ns range, 8-ps resolution, timing generator LSI utilizing Si bipolar gate array,” IEEE J. Solid-State Circuits, vol. 26, no. 5, pp. 806–811, May 1991.
[7] T. Okayasu, M. Suda, K. Yamamoto, S. Kantake, S. Sudou, and D. Watanabe, “1.83ps-resolution CMOS dynamic arbitrary timing generator for > 4 GHz ATE applications,” in Proc. IEEE ISSCC Dig., Feb. 2006, pp. 2122–2131.
[8] J. Christiansen, “An integrated high resolution CMOS timing generator based on an array of delay locked loops,” IEEE J. Solid-State Circuits, vol. 31, no. 7, pp. 952–957, Jul. 1996.
[9] T. Y. Wang, S. M. Lin, and H. W. Tsao, “Multiple channel programmable timing generators with single cyclic delay line,” IEEE Trans. Instrum. Meas., vol. 53, pp. 1295–1303, Aug. 2004.
[10] S. Henzler, Time-to-Digital Converters. Dordrecht, Netherland: Springer, 2010.
[11] Phillip E. Allen, Douglas R. Holberg, CMOS Analog Circuit Design, 2nd ed. New York: Oxford, 2010.
[12] H. Chung, H. Ishikuro, and T. Kuroda, “A 10-Bit 80-MS/s Decision-Select Successive Approximation TDC in 65-nm CMOS,” IEEE J. Solid-State Circuits, vol. 47, no. 5, pp. 1232–1241, May 2012.
[13] A. Van Den Bosch, M.A.F. Borremans, M.S.J. Katholieke, and W. Sansen, “A 10-bit 1-GSample/s Nyquist current-steering CMOS D/A converter,” IEEE J. Solid-State Circuits, vol. 36, no. 3, pp. 315–324, Mar. 2001.
[14] C. H. Lin and B. Klaas, “A 10-b, 500-MSample/s CMOS DAC in 0.6 mm2,” IEEE J. Solid-State Circuits, vol. 33, no. 12, pp. 1948–1958, Dec. 1998.
[15] M. J. M. Pelgrom, A. C. J. Duinmaijer, and A. P. G. Welbers, “Matching properties of MOS transistors,” IEEE J. Solid-State Circuits, vol. 24, no. 5, pp.1433–1440, Oct. 1989.
[16] G. W. Roberts and M. Ali-Bakhshian, “A Brief Introduction to Time-to-Digital and Digital-to-Time Converters,” IEEE Trans. Circuit Syst. II, Exp. Brief, vol. 57, no. 3, pp. 153–157, Mar. 2010.
[17] A. Mantyniemi, T. Rahkonen, and J. Kostamovaara, “A CMOS Time-to-Digital Converter (TDC) Based On a Cyclic Time Domain Successive Approximation Interpolation Method,” IEEE J. Solid-State Circuits, vol. 44, no. 11, pp.3067–3078, Nov. 2009.
[18] S. Al-Ahdab, A. Mantyniemi, and J. Kostamovaara, “Cyclic time domain successive approximation time-to-digital converter (TDC) with sub-ps-level resolution,” in Proc. IEEE International Instrumentation and Measurement Technology Conf. (I2MTC), May 2011, pp. 1–4.
[19] K. Kozmin, J. Johansson, and J. Delsing, “A low power, propagation delay stable, continuous-time comparator,” in Proc. NorChip Conf., Nov 2004, pp. 261–264.

2019-09-05公開

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