隨著製程發展，類比元件的效能會大大受限於短通道效應，因此，能夠減輕類比電路設計負擔的創新設計技巧或電路架構是很重要的。此論文提出一個使用分開資料加權平均演算法和逐漸逼近式量化器的一階低失真三角積分調變器，其具有低功耗、小面積以及高頻寬的優點。此三角積分調變器使用比較器式的放大器取代傳統運算放大器以降低放大器的設計困難度，並且採用低失真的架構來降低放大器的輸出訊號擺幅，以提升整體調變器的線性度。為了更降低整體的功耗，這次設計提出具有內建被動加法之低功耗逐漸逼近式量化器，免除訊號相加所使用的放大器。再者，這次設計還提出一個分開資料加權平均演算法來簡化數位電路，達到節省晶片面積的目的。
整個設計使用台積電90奈米1P9M互補式金氧半製程來實現晶片，其核心電路面積為0.0275平方毫米。在1伏特的電壓源、6千5百萬赫茲取樣頻率、50萬赫茲的輸入頻率量測環境下，量測結果達到59.90分貝的訊雜比，總消耗功率 0.58毫瓦特。

With the evolution of the modern process, the performance of analog components suffers from the severe short channel effects. Therefore, novel design techniques and architectures which are able to release the burden of analog design efforts is important. This thesis presents a first-order low distortion sigma-delta modulator (SDM) using split data-weighted-averaging (DWA) algorithm and successive-approximation register (SAR) quantizer to achieve low power, low area and wide bandwidth SDM. In this work, a comparator-based operational amplifier instead of the conventional one is utilized in the integrator to release the design complexity for operational amplifier in advanced process. In the meanwhile, a low distortion structure with small output swing can relax the design effort and improve the linearity of whole modulator. On the top of that, to reduce the power consumption, a power efficient SAR quantizer with embedded analog passive adder is proposed to eliminate additional operational amplifier for summation. Moreover, a proposed split DWA simplifies the digital control logic for higher resolution quantizer to save the silicon area.
The modulator core occupies an active area of 0.0275 mm2 in TSMC 90-nm 1P9M CMOS process. The experimental results show that the proposed modulator achieves 59.90 dB SNDR with 0.58 mW power consumption under 1.0 V supply voltage, an OSR of 16 at 65 MHz sampling frequency and 500kHz input frequency.

Reference
[1] W. Kester, “Which ADC architecture is right for your application ?,” http://www.analog.com/
[2] Alan V. Oppeheim, Alan S. Willsky, and S. Hamid Nawab “ Sampling” in Signals & Systems, 2th ed, Prentice-Hall, 2008, pp.516–555
[3] W. R. Bennett, “Spectra of Quantized Signals,” Bell System Technical Journal, vol. 27, pp. 446–471, July 1948
[4] A. B. Sripad and D. L. Snyder, “A Necessary and Sufficient Condition for Quantization Errors to be Uniform and White,” IEEE Transactions on Acoustics, Speech and Signal Processing , vol. 25, pp. 442-448, Oct 1977
[5] David A. Johns and Ken Martin, “Oversampling Converter” in Analog Integrated Circuit Design, Wiley,1997, pp. 531–571
[6] Richard Schreier, and Gabor C. Temes, Understanding Delta-Sigma Data Converters. Wiley-Interscience, 2005
[7] Franco Maloberti, Data Converter, Springer, 2007
[8] Jose M. de la Rosa and Rocio del Rio, CMOS Sigma-Delta Converters Practical Design Guide, Wiley, 2012
[9] R. van de Plassche, CMOS integrated Analog-to-Digital and Digital-to-Analog Converters, Springer, 2003.
[10] A. Marques, V. Peluso, M. S. Steyaert, and W. M. Sansen, “Optimal Parameters for ΣΔ Modulator Topologies,” IEEE Trans. Circuits Syst. II: vol. 45(9), pp. 1232–1241, Sep 1998.
[11] L. Breems and J. H. Huijsing, Continuous-Time Sigma-Delta Modulation for A/D Conversion in Radio Receiver, Kluwer Academic Publishers, 2001
[12] M. Ortmanns and F. Gerfers, Continuous-Time Sigma-Delta A/D Conversion: Fundamentals, Performance Limits and Robust Implementations, Springer, 2006
[13] J. Cherry and W. Snelgrove, “Clock jitter and quantizer metastability in continuous-time ΣΔ modulators,” IEEE Trans. Circuits Syst. II: Analog Digit. Signal Process., vol. 46, no. 6, pp. 661–676, 1999
[14] S. Luschas and H.-S. Lee, “High-speed modulators with reduced timing jitter sensitivity,” IEEE Trans. Circuits Syst. II: Analog Digital Signal Processing, vol. 49, no. 11, pp. 712–720, Nov. 2002.
[15] J. Cherry and W. Snelgrove, “Excess loop delay in continuous-time delta-sigma modulators,” IEEE Trans. Circuits Syst. II: Analog Digital Signal Processing, vol. 46, no. 4, pp. 376–389, Apr. 1999.
[16] S. Yan and E. Sanchez-Sinencio, “A continuous-time sigma-delta modulator with 88-dB dynamic range and 1.1-MHz signal bandwidth,” IEEE J. Solid-State Circuits, vol. 39, no. 1, pp. 75–86, Jan. 2004
[17] K. Nguyen, R. Adams, K. Sweetland, and H. Chen, “A 106-db SNR hybrid oversampling analog-to-digital converter for digital audio,” IEEE Journal of Solid-State Circuits, vol. 40, no. 12, pp. 2408–2415, 2005.
[18] P. Morrow et al., “A 0.18ȝm 102dB-SNR mixed CT SC audio-band ΣΔ ADC,” in IEEE ISSCC Digest of Technical Papers, February 2005, pp. 178–179.
[19] S. D. Kulchycki, R. Trofin, K. Vleugels, and B. A. Wooley, “A 77-dB dynamic range, 7.5-MHz hybrid continuous-time/discrete-time cascaded modulator,” IEEE J. Solid-State Circuits, vol. 43, no. 4, pp. 796–804, Apr. 2008.
[20] Y. Muhuya, K. Uchimura, K. Iwala, T. Yoshitome, et al., “A 16-bits oversampling A-to-D conversion technology using help integration noise shaping,” IEEE J. Solid-State Circuits, vo1.36. pp. 800–809. May 1987
[21] N. Maghari and U. Moon, “Multi-loop efficient sturdy MASH delta-sigma modulators,” Proc. ISCAS, May 2008, pp. 1216–1219.
[22] Y. Greets, M. Stetaert, and W. Sansen, Design of Multi-bit Delta-Sigma A/D Converters, Kluwer Academic Publishers, 2002
[23] J. Li, Un-Ku Moon, “Background calibration techniques for multistage pipelined ADCs with digital redundancy,” IEEE Trans. Circuits Syst. II: Analog and digital signal processing, vol. 50, no. 9, pp.531–538, September 2003.
[24] Ferragina, V. et. al, “Gain and offset mismatch calibration in time-interleaved multipath A/D sigma-delta modulators,” IEEE Trans. Circuits Syst. I: Regular Papers, vol.51, no.12, pp. 2365–2373, Dec. 2004
[25] J. van de Plassche, “Dynamic element matching for high accuracy monolithic D/A converters,” IEEE J. Solid-State Circuits, vol. 11, no. 6, pp. 795–800, Dec. 1976
[26] L.R. Carley and J. Kenney, “A 16-Bit 4th Order Noise-Shaping D/A Convener,” IEEE Custom Integrated Circuits Conference, pp. 21.7.1–21.7.4, May 1988.
[27] B. Leung and S. Sutarja, “Multi-bit Δ-Σ Converter Incorporating a Novel Class of Dynamic Element and Matching Technique,” IEEE Trans. Circuits Syst. II: Analog and digital signal processing, vol. 39, no. 1, pp.35–51, Jan 1992.
[28] R. T. Baird and T. S. Fiez, “Linearity enhancement of multi-bit ΔΣ A/D and D/A converters using data weighted averaging,” IEEE Trans. Circuits Syst. II, Analog Digit. Signal Process., vol. 42, no. 12, pp. 753–762, Dec. 1995
[29] S. A. Jantzi, K. W. Martin, and A. S. Sedra, “Quadrature bandpass delta sigma modulation for digital radio,” IEEE J. Solid-State Circuits, vol. 32, no. 12, pp. 1935–1950, Dec. 1997.
[30] J. Ryckaert, J. Borremans, B.Verbruggen, et al, “A 2.4 GHz low-power sixth-order RF bandpass ΣΔ converter in CMOS,” IEEE J. Solid-State Circuits, vol. 44, no. 11, pp. 2873–2880, Nov. 2009.
[31] J. Harrison, M. Nesselroth, R. Mamuad, A. Behzad, A. Adams, and S. Avery, “An LC bandpass Delta-Sigma ADC with 70dB SNDR over 20MHz bandwidth using CMOS DACs,” IEEE ISSCC Digest of Technical Papers, Feb 2012, pp. 146–147.
[32] H. Chae, J. Jeong, G. Manganaro, and M. Flynn, “A 12mW Low-power Continuous-time Bandpass ΔΣ Modulator with 58dB SNDR and 24MHz Bandwidth at 200MHz IF,” IEEE ISSCC Digest of Technical Papers, Feb 2012, pp. 148–150.
[33] K. B. Klaasen “Digitally Controlled Absolute Voltage Division” IEEE Transactions on Instrumentation and Measurement, vol. 24, issue 2, pages 106–112, June 1975
[34] R. E. Radke, A. Eshraghi, and T. S. Fiez, “A 14-bit current-mode ΔΣ DAC based upon rotated data weighted averaging,” IEEE J. Solid-State Circuits, vol. 35, no. 8, pp. 1074–1084, Aug. 2000.
[35] M. Vadipour, “Techniques for Preventing Tonal Behavior of Data Weighted Averaging Algorithm in Σ-∆ Modulators”, IEEE Trans. Circuits Syst. II: Analog and digital signal processing, vol. 47, no. 11, pp. 1137–1144, Nov. 2000.
[36] I. Fujimori, L. Longo, A. Hairapetian, K. Seiyama, S. Kosic, J. Cao, and S. Chan, “A 90-dB SNR 2.5-MHz output rate ADC using cascaded multibit Delta-Sigma modulation at 8×oversampling ratio,” IEEE J. Solid-State Circuits, vol. 35, no. 12, pp. 1820–1828, Dec. 2000.
[37] K. Vleugels, S. Rabii, and B.A. Wooley “A 2.5-V Sigma-delta Modulator for Broadband Communications Applications,” IEEE J. Solid-State Circuits, vol. 36, no. 12, pp. 1887–1899, Dec. 2001.
[38] A. A. Hamoui and K. Martin, “Linearity Enhancement of Multibit ΔΣ Modulators Using Pseudo Data-Weighted Averaging,” in Proc. IEEE ISCAS, May 26–29, 2002, vol. 3, pp. III-285–III-288.
[39] R. K. Henderson and O. J. A. P. Nys “Dynamic Element Matching Techniques with Arbitrary Noise Shaping Function” in Proc. IEEE ISCAS, May 12–15, 1996, vol. 1, pp. 293–296.
[40] R. Schreier, and B. Zhang “Noise-shaped multibit D/A converter employing unit elements” Electron. Lett., vol. 31, no. 20, pp. 1712–1713 Sept. 1995.
[41] I. Galton “Spectral shaping of circuit errors in digital-to-analog converters” IEEE Trans. Circuits Syst. II: Analog and digital signal processing, vol. 44, no. 10, pp 808–817, Aug. 2002.
[42] J. Silva, U.K. Moon, J. Steensgaard, and G.C. Temes, “Wideband low-distortion delta-sigma ADC topology,” Electron. Lett., col. 37, pp. 737–738. Jun. 2001.
[43] A. Gharbiya and D. A. Johns, “On the implementation of input-feedforward delta-sigma modulators,” IEEE Trans. Circuits Syst. II: Exp. Briefs, vol. 53, pp. 453–457, Jun. 2006.
[44] K. Lee and G. C. Temes, “Improved low-distortion ΔΣ ADC Topology,” in Proc. IEEE Int. Symp. Circuits and Syst., May 2009, pp. 1341–1344.
[45] Y. Fujimoto, Y. Kanazawa, P. L. Re, and M. Miyamoto, “An 80/100MS/s 76.3/70.1dB SNDR ΔΣ ADC for digital TV receivers,” IEEE ISSCC Digest of Technical Papers, Feb. 2006, pp. 76–77.
[46] W. Shen and G. C. Temes, “Double-sampled ΔΣ modulator with relaxed feedback timing,” in Proc. IEEE Int. Midwest Symp. Circuits and Syst., Aug. 2009, pp. 393–396.
[47] Fiorenza, J.K. Sepke, Hae-Seung Lee, et al. “Comparator-Based Switched-Capacitor Circuits for Scaled CMOS Technologies,” IEEE J. Solid-State Circuits, vol. 41, pp. 2658–2668, Dec. 2006.
[48] Chun-Cheng Liu, Soon-Jyh Chang, Guan-Ying Huang, et al. “A 10-bit 50-MS/s SAR ADC with a Monotonic Capacitor Switching Procedure,” IEEE J. Solid-State Circuits, vol.45, no.4, pp.731–740, Apr. 2010.
[49] Richard Schreier, José Silva, , Jesper Steensgaard, and Gabor C. Temes, “Design-Oriented Estimation of Thermal Noise in Switched-Capacitor Circuits” IEEE J. Solid-State Circuits, vol.52, no.11, pp.2358–2368, Dec. 2005.
[50] K. Bult and G. J. G. H. Geelen, “A Fast CMOS Operational Amplifier for SC Circuits with 90-dB DC Gain,” IEEE J. Solid-State Circuits, vol.25, pp.1379–1384, Dec. 1990.
[51] E. Sackinger and W. Guggenbuhl, “A High-Swing High-Impedance MOS Cascode Circuit.” IEEE J. Solid-State Circuits, vol.25, pp.289–298, Feb. 1990.
[52] S. Yan and E. Sanchez-Sinencio, “Low Voltage Analog Circuit Design Techniques: A Tutorial,” IEICE Trans. Analog Integrated Circuits and Systems, pp. 1–17, Feb. 2000.
[53] E. Siragusa and I. Galton “A digitally enhanced 1.8-V 15-bit 40-MSample/s CMOS pipelined ADC”, IEEE J. Solid-State Circuits, vol. 39, no. 12, pp.2126–2138, Dec. 2004
[54] Y. Chae and G. Han, “Low voltage, low power, inverter-based switched-capacitor delta-sigma modulator”, IEEE J. Solid-State Circuits, vol. 44, no. 2, pp.458–472, Feb. 2009
[55] B. Hershberg, Weaver, S, Un-Ku Moon et al., “Ring Amplifiers for Switched Capacitor Circuits,” IEEE J. Solid-State Circuits, vol. 47, no. 12, pp.2928–2942, Dec. 2012
[56] A. Iwata, N. Sakimura, M. Nagata, and T. Morie, “An architecture of delta sigma A-to-D converters using a voltage controlled oscillator as a multi-bit quantizer,” IEEE Transactions on Circuits and Systems II, vol. 46, issue 7, pp. 941–945, July 1999.
[57] G. Taylor and I. Galton, “A Mostly-Digital Variable-Rate Continuous-Time Delta-Sigma Modulator ADC,” IEEE J. Solid-State Circuits, vol. 45, pp. 2634–2646, Dec. 2010.
[58] M. Dessouky, and A. Kaiser, “Input switch configuration for rail-to-rail operation of switched opamp circuits,” Electronics Letters, vol. 35, no. 1, pp. 8–10, Jan 1999
[59] Lane Brooks, and Hae-Seung Lee, “A 12b, 50 MS/s, Fully Differential Zero-Crossing Based Pipelined ADC,” IEEE J. Solid-State Circuits, vol. 44, no. 12, pp.3329–3343, Dec. 2009
[60] S. W. M. Chen and R. W. Borderson, “A 6-bit 600MS/s 5.3Mw Asynchronous ADC in 0.13µm,” IEEE J. Solid-State Circuits, vol. 41, no. 12, pp.2669–2680, Dec. 2006
[61] Y. D. Jeon, Y. K. Cho, J. W. Nam, et al. “A 9.15mW 0.22mm2 10b 204MS/s pipelined SAR ADC in 65nm CMOS,” IEEE Custom Integrated Circuits Conference, Sep. 2010, pp. 1–4
[62] B. Verbruggen, J. Craninckx, M. Kuijk, et al. “A 2.6mW 6b 2.2GS/s 4-times interleaved fully dynamic pipelined ADC in 40nm digital CMOS,” IEEE International Solid-State Circuits Conference, Feb. 2010, pp. 296–297
[63] Z. Chen, Y. Jiang, C. Cai, H. G. Wei, S. W. Sin, S. P. U, Z. Wang, and R. P. Martins, "A 22.4 uW 80dB SNDR sigma-delta modulator with passive analog adder and SAR quantizer for EMG application," in Proc. Asia Solid-State Circuits Conf., Nov. 2012, pp. 257–260.
[64] M. van Elzakker, E.van Tuijl, and P. Geraedts, et al. “A 1.9μW 4.4fJ/Conversion-step 10b 1MS/s Charge-Redistribution ADC,” IEEE International Solid-State Circuits Conference, Feb. 2008, pp. 244–610
[65] Y. Zhu, C.-H. Chan, U-F. Chio, S.-W. Sin, S.-P. U R. P. Martins and F. Maloberti, “A 10-bit 100-MS/s Reference-Free SAR ADC in 90nm CMOS,” IEEE J. Solid-State Circuits, vol. 45, pp. 1111–1121, June 2010.
[66] C.-C. Liu, S.-J. Chang, G.-Y. Huang, Y.-Z. Lin, C.-M. Huang, C.-H. Huang, L.-K. Bu and C.-C. Tsai, “A 10b 100MS/s 1.13mW SAR ADC with Binary-Scaled Error Compensation” IEEE ISSCC Digest of Technical Papers, Feb. 2010, pp. 386–387.p
[67] G.-Y. Huang, S.-J. Chang, Y.-Z. Lin, C.-C. Liu, and C.-P. Huang, “A 10b 200MS/s 0.82mW SAR ADC in 40nm CMOS, ” in Proc. Asia Solid-State Circuits Conference., Nov. 2013, pp. 289-292.
[68] S.-H. Lin, “A Pipelined SAR ADC with Loading-Separating Technique for Residue Amplification,” M.S. thesis, Dept. Elect. Eng., Cheng Kung Univ., Tainan, Taiwan, 2012.
[69] P. Harpe, C. Zhou, X. Wang, G. Dolmans, and H. de Groot, “A 12fJ/conversion-step 8bit 10MS/s asynchronous SAR ADC for low energy radios,” in Proc. ESSCIRC, 2010.
[70] T. Musah, S. Kwon, H. Lakdawala, K. Soumyanath, and Un-Ku Moon, “A 630μW Zero-Crossing-Based ΔΣ ADC Using Switched-Resistor Current Sources in 45nm CMOS,” IEEE Custom Integrated Circuits Conference, Sept. 2009, pp1-4.
[71] J. Zhang, L. Yao, Y. Lian, “A 1.2-V 2.7-mW 160MHz Continuous-Time Delta-Sigma Modulator with Input-Feedforward Structure” IEEE Custom Integrated Circuits Conference, Sept. 2009, pp 475-478.
[72] M. Ranjbar, A. Mehrabi, O. Oliaei, F. Carrez, “A 3.1 mW Continuous-Time ΔΣ Modulator With 5-Bit Successive Approximation Quantizer for WCDMA” IEEE J. Solid-State Circuits, vol. 41, no. 12, pp.1479–1491, Aug. 2010.
[73] L. Bos, G. Vandersteen, P. Rombouts, A. Geis, A. Morgado, Y. Rolain, G. V. Plas and J. yckaert, “Multirate cascaded discrete-time low-pass ΔΣ modulator for SM/Bluetooth/UMTS,” IEEE J. Solid-State Circuits, vol. 45, pp. 1198–1208, June 2010.
[74] K. Yamamoto, A.C. Carusone, “A 1-1-1-1 MASH Delta-Sigma Modulator with Dynamic Comparator-Based OTAs,” IEEE J. Solid-State Circuits, vol. 47, pp. 1866-1883, Oct. 2012.
[75] Taehwan Oh, Maghari N, Un-Ku Moon, “A Second-Order ΔΣ ADC Using Noise-Shaped Two-Step Integrating Quantizer,” IEEE J. Solid-State Circuits, vol. 48, pp. 1465–1474, Oct. 2013.
[76] K. Lee, Y. Yoon, N. Sun, “A 1.8mW 2MHz-BW 66.5dB-SNDR Delta-Sigma ADC Using VCO-Based Integrators with Intrinsic CLA,” IEEE Custom Integrated Circuits Conference, Sept. 2013, pp1–4.
[77] C.-H. Weng, T.-A. Wei, E. Alpman, C.-T. Fu, Y.-T. Tseng, and T.-H. Lin “An 8.5MHz 67.2dB SNDR CTDSM with ELD Compensation Embedded Twin-TSAB and Circular TDC-based Quantizer in 90nm CMOS” IEEE Symp. VLSI Circuits, pp. 87–88 Jun, 2014.