| 研究生: |
蔡順帆 Tsai, Shun-fan |
|---|---|
| 論文名稱: |
基於砌塊式繪圖架構之三維繪圖幾何引擎設計、分析與實現 Design, Analysis, and Implementation of a Geometry Engine Based on Tile-Based Rendering Architecture in 3D Graphics |
| 指導教授: |
陳中和
Chen, Chung-ho |
| 學位類別: |
碩士 Master |
| 系所名稱: |
電機資訊學院 - 電腦與通信工程研究所 Institute of Computer & Communication Engineering |
| 論文出版年: | 2009 |
| 畢業學年度: | 97 |
| 語文別: | 中文 |
| 論文頁數: | 111 |
| 中文關鍵詞: | 幾何引擎 、電腦圖學(繪圖) 、Tile-Based 繪圖管線 |
| 外文關鍵詞: | Computer graphics, Geometry engine, Tile-based rendering pipeline |
| 相關次數: | 點閱:204 下載:2 |
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本篇論文提出一個基於砌塊式繪圖管線架構之Geometry引擎。在3D電腦繪圖中,其所描述的場景由幾何單元所表示,也就是點、線、面,而這些幾何單元再依照光源的設定繪製出受不同光源影響的顏色圖像。而本篇論文則根據OpenGL ES 1.1的規格設計一個處理幾何單元運算的Geometry引擎並對並對其硬體架構作進一步的效能評估及分析。
在Geometry引擎的設計上,頂點處理器的架構切割成兩大級管線,有效地提升硬體使用率,減少面積;另外將perspective division模組設計於頂點處理器內,與未改善前的架構相比,整體面積降低58.6%。光源的指數計算部份以內插法的方式設計查表並將其實現成硬體,與未改善前的硬體合成面積相比,降低了17倍。為了減少匯流排頻寬,除了設計Culling模組外,我們提出ATT (Abandon Tiny Triangles)演算法刪除微小三角形,減少50%至60%不會繪製在螢幕上的三角形輸出量。此Geometry引擎在0.18um的製程下總共佔389K個邏輯閘,且能在200MHz的工作頻率下正確執行,並有瞬間最高7.407M Tri/sec的三角形運算效能。此硬體在QEMU結合CoWare的完整系統模擬環境下,能完整地驗證ARM嵌入式系統經由啟動Linux並執行OpenGL ES的應用程式。
This thesis presents a Geometry engine based on a tile-based rendering architecture. In 3D computer graphics, the scene is typically constructed from geometry objects made up from vertices, lines, or triangles, and these geometry objects are displayed in different types by various drawing modes. We design a Geometry engine that deals with the geometry calculation according to OpenGL ES 1.1 specifications and evaluate the performance of the hardware architecture.
In Geometry engine designing, we split the vertex processor into a 2-stage pipeline in order to reduce the overall area cost by increasing the hardware utilization efficiently. Comparing with the traditional architecture, we propose a new architecture that puts the perspective division model in the vertex processor. This design results in overall area reduction by 58.6%. For the lighting model, we use a linear interpolation index-reduced method to design the lookup table, and the synthesis area is nearly 17 times smaller than the hardware without modification. In order to reduce the bus traffic, we design a Culling model and propose an ATT (Abandon Tiny Triangles) algorithm to discard tiny triangles. The total triangle reduction is about 50% to 60% that would not be rendered on the screen. The Geometry engine has been realized by 0.18 um technology and the total gate count is 389K. It can run up to 200 MHz, and deliver the peak fill rate of 7.407M Tri/sec. It has been simulated and verified with OpenGL ES applications executed on Linux in an ARM embedded system modelled by a full system simulation platform which combines QEMU and an ESL tool.
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