此研究承續了本實驗室的研究成果，發展出生理肌電訊號辨識核心晶片，藉由分析肌電圖訊號來判斷出肢體障礙者所做之動作，辨識指揮命令並且做出控制訊號，做為癱瘓患者與電子輔助設備間之人機溝通介面。本論文以超大型積體電路之設計方式實現了生理肌電圖辨識系統晶片，使用圖形辨識的技術，將肌電圖訊號的倒頻譜(cepstral)參數做為特徵值，並且利用動態時間校準做為辨識演算法。在晶片設計上使用單時脈設計和折疊架構方式，以減少運算單元，達到縮小面積、降低成本和即時辨識的需求，經由TSMC 0.18 um Mixed signal CMOS製程下線成功，core size為0.887 x 0.887 mm2，chip size為1.837 x 1.837 mm2，並且在晶片之中加入了掃描鏈設計(scan chain)以增加晶片的可測試性。本晶片通過國家晶片系統設計中心的高階混合訊號自動測試系統「Agilent 93000 SOC Test System」之完整測試，量測結果驗證模擬結果與晶片功能一致，並將晶片整合於外部系統電路，完成了生理肌電訊號辨識晶片之系統雛型。

This study presents a surface electromyogram (EMG) recognition chip. The EMG signals picked up from the intact musculature during volitional motion can be analyzed by the EMG recognition chip as a control interface between the handicapped people and bioelectronics auxiliary tools. This EMG recognition chip was developed as an application-specific integrated circuit (ASIC). An EMG pattern-recognition algorithm composed of a cepstrum extraction core and a dynamic warping core is mapped in this system. A single clock design and floded architecture are adopted to reduce the chip area for low cost and real-time recognition. This chip is fabricated using 0.18 um CMOS single-poly six-metal technology on a die sized 0.887 x 0.887 mm2 and was fully tested via the Agilent 93000 SOC Test System at the national chip implementation center (CIC). The memory build-in-self-test (BIST) and scan chain are designed for testability. Test results verify the consistency between hardware description language simulations and chip function measurement results. The prototype of the surface EMG recognition system is composed of the EMG recognition chip and a system circuit board.

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