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研究生: 洪宗緯
Hung, Tsung-Wei
論文名稱: 高能源效率之區塊式可擴充性蒙哥馬利乘法器
Energy-efficient Block-based Scalable Montgomery Multiplication Design
指導教授: 謝明得
Shieh, Ming-Der
學位類別: 碩士
Master
系所名稱: 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年: 2013
畢業學年度: 101
語文別: 中文
論文頁數: 60
中文關鍵詞: 密碼學系統高能量效率設計蒙哥馬利乘法可擴充性設計超大型積體電路
外文關鍵詞: cryptosystems, energy-efficient design, Montgomery modular design, scalable architecture, VLSI
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  • 現今透過行動裝置對網路存取資料,傳輸個人訊息的安全機密顯得日益重要。例如手機因為受限於電池容量,因此需要一個節能的密碼學系統來保護訊息傳輸。模乘法運算廣泛地應用在公開金鑰密碼學系統。故此篇論文將介紹一個高能源效率之區塊式可擴充性蒙哥馬利乘法器。
    提出映射至硬體架構的方式以及延遲資料處理的技巧。不僅減少核心管線化暫存器的切換邏輯閘次數以及外部記憶體存取次數,同時亦能支援任意運算元長度的蒙哥馬利乘法運算。實現結果使用台灣積體電路製造公司提供的90奈米製程資料,與其他文獻相比,一旦處理更大的運算元長度,造成所有核心處理單元無法平行化處理運算字元總數的狀況下,即可證實我們提出的高能源效率之蒙哥馬利乘法器處理一次蒙哥馬利乘法運算,能量耗損比其他文獻擁有8.2%至59.1%的減少幅度。

    Nowadays, security requirements are increasingly important for private data transmission through mobile devices with Internet access, such as smart phones, which require an energy-efficient cryptosystem due to the limitation of battery capacity. Modular multiplication is widely used in public key cryptosystems. This thesis presents an energy-efficient block-based scalable Montgomery modular multiplication design.
    Using the proposed architecture mapping scheme and deferred scheme in dependency graph, not only reduces the switching activity of pipeline registers in kernel and memory access, but also supports any precision of operands. Experimental results based on TSMC 90-nm CMOS technology show that compared to the related works under the number of words larger than the number of processing elements, the proposed design achieves 8.2% to 59.1% energy reduction than related work for completing one Montgomery modular multiplication.

    摘  要 iii ABSTRACT iv 誌  謝 v 表 目 錄 viii 圖 目 錄 ix 第一章 緒論 1 1.1 研究動機 1 1.2 論文架構 2 第二章 背景知識介紹 4 2.1 公開金鑰密碼學系統模型 4 2.1.1 RSA公開金鑰密碼學系統 5 2.1.2 橢圓曲線公開金鑰密碼學系統 6 2.2 蒙哥馬利乘法演算法簡介 9 2.2.1 模運算的數學性質 9 2.2.2 基底二蒙哥馬利乘法演算法 9 2.2.3 蒙哥馬利領域與實數領域的轉換 10 2.3 互補式金氧半導體電路功率耗損之簡介 11 2.4 相關研究綜述 12 2.4.1 以字元為基準可擴充性蒙哥馬利乘法演算法 12 2.4.2 運算元左移之蒙哥馬利乘法演算法 12 2.4.3 低延遲技術之可擴充性蒙哥馬利乘法演算法 12 2.4.4 低記憶體頻寬之可擴充性蒙哥馬利乘法演算法 14 第三章 提出的高能源效率之區塊式可擴充性蒙哥馬利乘法演算法 15 3.1 高能源效率之蒙哥馬利乘法器設計方法 15 3.2 區塊式處理之可擴充性蒙哥馬利乘法演算法 16 3.2.1 區塊內部資料之處理 24 3.2.2 區塊邊界資料之處理 26 3.3 比較與分析 33 3.3.1 資料相依圖映射至硬體之時程排序 33 3.3.2 外部記憶體存取次數與內部管線化暫存器切換邏輯閘次數 37 第四章 硬體架構之設計與實現驗證 40 4.1 硬體架構 40 4.1.1 蒙哥馬利乘法器之整體硬體架構 40 4.1.2 各個運算元所需之記憶體大小空間的探討 42 4.1.3 核心處理單元與區塊邊界處理單元之設計 44 4.2 硬體複雜度分析 47 4.2.1 關鍵的資料路徑之評估 47 4.2.2 面積成本之評估 49 4.3 驗證方法 50 4.4 實現結果與比較 52 第五章 結論與未來展望 58 5.1 結論 58 5.2 未來展望 58 參考文獻 59

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