本論文提出了一種基於晶片上環形振盪器（RO）的延遲測量方法，用於3DIC的矽穿孔（TSVs）。由於環形震盪器之閉迴路延遲對微小變化的高靈敏度，此方法的解析度非常高。在這個方法中，每個TSV的延遲都可以由四個閉迴路組成的環型震盪器的振盪周期中精確地推導出來。其主要想法是消除閉迴路上與TSV無關的邏輯元件的延遲，包括與TSV相連的驅動器和多工器的延遲。我們定義了三個符號來表示三種類型的環形震盪器閉迴路的振盪周期。這使我們能夠有系統性地消除所有閘延遲，僅留下TSV的延遲。實驗結果表明，我們的測量結果可以達到幾皮秒(ps)的解析度。我們還進行了蒙地卡羅模擬，以納入製程變異的影響。實驗結果顯示我們的方法與SPICE模擬之間TSV延遲的最大誤差僅為0.19 ps，誤差率為5.86%。這些結果證明了實現了TSV延遲測量的高解析度和高準確度。

This thesis presents an on-chip, ring-oscillator (RO) based delay measurement scheme for the through silicon vias (TSVs) of 3DIC. The resolution is very high due to the high sensitivity of the RO period on the subtle change in the RO closed loop delay. In this scheme, each TSV’s delay can be accurately derived from the oscillation periods of four closed RO loops. The key idea is to cancel out the delays of logic components on the closed loops, including the drivers and the multiplexers connected to the TSV. We define three notations to represent the oscillation periods of three types of RO loops. This enables us to systematically cancel out all gate delays and leave only the routing delays of TSVs. Experimental results show that our measurement results can achieve the resolution of a few picoseconds. We also carry out Monte Carlo simulations to incorporate the effects of process variations. The results show that the maximum error of TSV delays between our method and SPICE simulations is only 0.19ps, which is an error ratio of 5.86%. These results demonstrate that high resolution and high accuracy on TSV delay measurement are achieved.

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