本論文提出一個可以應用於高壓系統整合之寬輸入振幅逐漸趨近式類比數位轉換器。
在高壓系統中，類比至數位轉換器面臨到的問題是輸入訊號之振幅和輸入共模電壓超過其可接受的範圍，為了解決這個問題，一般會在類比至數位轉換器之前端加入一個可程式增益放大器(Programmable Gain Amplifier)來調整輸入訊號之振幅以滿足類比至數位轉換器之輸入動態範圍(Input Dynamic Range)。然而，可程式增益放大器由於內部必須使用到運算放大器，並且操作於高電壓，勢必會消耗掉不少的能量。本論文提出名為內建振幅衰減之取樣技術，透過加入一個新式的前端取樣電路並與逐漸趨近式類比數位轉換器做結合，如此一來既能接收寬輸入振幅之訊號且可大量節省了可程式增益放大器所消耗的能量。本論文所提出的內建振幅衰減取樣電路是由開關切換電路(Switched-Capacitor Circuit)所實現且不需要使用到高壓元件，並容易與逐漸趨近式類比數位轉換器做整合。
在本論文中，以台積電180奈米製程研製一個使用內建振幅衰減技術的十一位元逐漸趨近式類比數位轉換器的測試晶片，其電路核心面積約為0.41mm2。此類比至數位轉換器在1.8伏特的電壓供應下操作在二千萬赫茲的取樣頻率(20-MS/s)。實測效能顯示，在1.8伏特電源供電及每秒取樣二千萬次的操作速度下，訊號雜訊比之最大值為63.14分貝，換算之有效位元數為10.2位元，消耗功率為1.82 mW，每次資料所消耗的能量為77.36fJ。

This thesis presents a wide input range successive-approximation register (SAR) analog-to-digital converter (ADC), which can be easily integrated into high-voltage systems.
For a low-supply-voltage ADC integrated in high-voltage systems, one of the major problems is that the swing of the input signal and the input common-mode voltage exceed its acceptable range. A programmable gain amplifier (PGA) is typically used in front of the ADC for adjusting the swing of the input signal level to meet the input dynamic range of ADC. However, it may require a power-hungry operational amplifier (opamp) to implement the PGA, and therefore degrade the power efficiency of the whole system.
This thesis proposes a new sampling technique named as “built-in swing attenuation.” By integrating the new front-end sampling circuit with a SAR ADC, it is able to deal with high voltage input signal without using power-hungry programmable gain amplifier. The front-end sampling circuit is implemented by switched-capacitor (SC) circuit without high voltage devices, which is low power, compact and easy to integrate with the SAR ADC.
The proof-of-concept 11-bit wide input range SAR ADC occupies 0.41mm2 in 180nm CMOS process. It operates at 20-MS/s with 1.8 V supply voltage. The measurement results show that the peak signal-to-noise and distortion ratio (SNDR) is 63.14 dB at 1.8 V supply and 20-MS/s sampling rate. The resultant effective number of bits is 10.2 bits with power consumption of 1.82 mW. The figure-of-merit (FoM) is 77.36 fJ/conversion-step.

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