The Discrete Wavelet Transform (DWT) has been used in image processing for the past few years. 2-D DWT architectures can be classified into line-based and block-based architectures. Line-based architectures are simple with low complexity. They are efficient for 1-D applications. In case of 2-D transforms (or higher), they suffer from two main problems: memory requirements and latency. These problems are inherent to line-based architectures. In this thesis, a novel block-based architecture for computing the lifting-based 2-D DWT coefficients is presented. These architectures make the significant reduction of buffer size and speeds up the calculation of 2-D wavelet coefficients as compared with those line-based fashion architectures. In addition, the proposed architecture supports the JPEG2000 default filters. Compared to the line-based architectures, the latency is reduced from N2 down to 3N. Finally, the architecture has been realized in ARM-based ALTERA EPXA10 Development Board with frequency at 44.33MHz.

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