在本篇論文中，我們提出JPEG影像解碼硬體化的設計，JPEG的解碼設計流程首先是JPEG標頭的處理，接著處理可變長度解碼以及反量化，再經由反Zig-Zag掃描將資料重新排列，並使用二維離散餘弦逆轉換將資料由頻率域的值轉回空間域的值，最後則是將YCbCr的色彩座標值轉回RGB色彩座標值，上述部分均由硬體描述語言(Verilog)完成。JPEG讀檔掃描，以及解碼後的RGB資料加入BMP標頭檔使之成為BMP影像這兩部分則是高階程式語言(C language)完成。
由實驗的數據中得知JPEG硬體解碼的速度比軟體解碼的速度平均快了2.9至4.3倍左右，當輸入的圖片像素越大時，表示需要做YCbCr轉RGB的資料量越大，相對效能提升的效果也越好。

In this paper, we propose hardware design for JPEG image decoder. The design process of decoder is handled JPEG header file. Then it handled variable length decoding and inverse quantization. We use inverse zig-zag scan rearrange the data, and use the two-dimensional inverse discrete cosine transform the data from the frequency domain values back to the apace domain values. Finally, it transformed YCbCr coordinate values into RGB coordinate values. The foregoing are completed by hardware description languages (Verilog). JPEG read file, and the data of RGB after decoding is added BMP header file let it became BMP image. The two parts are completed by high level language(C language).
According to the experimental data, the average speedup of the hardware JPEG decoder is about 2.9 to 4.3 times more than that of the software JPEG decoder. The larger the pixels of the input JPEG image are, the better the performance will be, particularly during the transformation from YcbCr to RGB.

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