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研究生： 寸恩澤
Cun, En-Ze
論文名稱： 一個基於只有前置放大的比較器之十位元每秒取樣三億次逐漸趨近式類比數位轉換器
A 10-bit 300-MS/s Successive-Approximation Analog-to-Digital Converter with a Pre-amplifier-only Comparator
指導教授： 張順志
Chang, Soon-Jyh
學位類別： 碩士
Master
系所名稱： 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年： 2019
畢業學年度： 107
語文別： 英文
論文頁數： 113
中文關鍵詞： 逐漸趨近式類比數位轉換器 、非二進位演算法 、多組比較器 、只有前置放大器的比較器 、高增益的動態前置放大器
外文關鍵詞： Successive approximation register (SAR) analog-to-digital converter (ADC), redundancy (or non-binary) algorithm, multiple comparators, pre-amplifier-only comparator, high-gain dynamic pre-amplifier
相關次數： 點閱：152  下載：19 
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    • 本論文呈現一個使用40奈米製程所研製之單通道十位元每秒取樣三億次的逐漸趨近式類比數位轉換器。
    我們提出了一種用於高速逐漸趨近式類比數位轉換器的粗細解析混合架構。在前面粗解析的位元循環裡，我們採用可提升速度的迴圈展開式技巧，在後面細解析中，我們採用了一個只使用前置放大器作為比較器的時序方案來提高操作速度。此外，我們採用非二進位的搜尋演算法來容忍粗細解析位元循環之間的不匹配，以維持整體性能。再者，也採用了反切電容切換方法，以提高比較速度。藉由上述所提的技巧，實現了高速的逐漸趨近式類比數位轉換器。
    本設計以台積電40奈米CMOS標準1P9M製程實作晶片，其核心電路面積佔了0.0289 mm2。量測結果顯示，在1.1伏特電源供應及每秒三億次的取樣頻率下，消耗功率為4.67 mW；在沒有使用複雜的校正電路下，最高的有效位元為9.36位元，每次的資料轉換所消耗的能量為23.6 fJ。

    A single-channel 10-bit 300-MS/s successive-approximation register (SAR) analog-to-digital converter (ADC) in 40-nm CMOS process is presented in this thesis.
    We propose a hybrid architecture with one common DAC to implement a high-speed SAR ADC. The operation speed is enhanced by adopting the loop-unrolled technique in the coarse conversions, and timing control scheme with pre-amplifier-only comparator technique in the fine conversions. Considering the mismatch between coarse and fine conversions, we adopt the non-binary search scheme with redundancy to maintain the overall performance. Moreover, switchback capacitor switching method is also used, which increases the speed of the comparison. With the above-mentioned techniques, it leads to a high-speed SAR ADC.
    The proof-of-concept prototype was fabricated in a TSMC 40-nm CMOS technology. The core area occupies 0.0289 mm2. At a supply voltage of 1.1-V and sampling rate of 300-MS/s, the power consumption of the SAR ADC is 4.67 mW and the peak ENOB is 9.36 bits. It achieves a figure of merit (FoM) of 23.6 fJ/conversion-step.

    摘　要 III Abstract IV List of Tables IX List of Figures X List of Abbreviations XIV Chapter 1 Introduction 1 1.1 Motivation 1 1.2 Organization of the Thesis 4 Chapter 2 Design Considerations for High-speed SAR ADCs 5 2.1 Basics of SAR ADCs 5 2.1.1 Sampling Phase 7 2.1.2 Conversion Phase 7 2.2 Speed Limitations for SAR ADCs 8 2.2.1 Comparison Time 9 2.2.2 DAC Settling Time and Comparator Resetting Time 14 2.2.3 Digital Circuit Gate Delay 17 Chapter 3 Design Techniques for High-speed SAR ADCs 20 3.1 Introduction 20 3.2 Timing Control Schemes 21 3.3 Simplified Digital Control Circuits 24 3.4 Sub-ranging Architectures 29 3.5 Multi-comparator Architectures 38 3.6 Capacitor Switching Methods 42 3.6.1 Conventional Capacitor Switching Procedure 43 3.6.2 Monotonic Capacitor Switching Procedure 45 3.6.3 SwitchBack Capacitor Switching Procedure 47 3.7 Error Tolerance of SAR ADCs 49 3.7.1 Binary Search algorithm 50 3.7.2 Redundancy Search algorithm 52 3.7.3 Types of Redundancy SAR ADCs 58 Chapter 4 A 10-bit 300-MS/s SAR ADC 60 4.1 Introduction 60 4.2 Architecture Consideration 61 4.2.1 Hybrid Coarse Fine SAR ADC Architecture 61 4.2.2 Timing Control scheme with Pre-amplifier-only Comparator 64 4.2.3 Dynamic High-gain Pre-amplifier 68 4.2.4 Redundancy Algorithm Design Consideration 71 4.2.5 Switchback Switching Method 74 4.3 Architecture of the Proposed SAR ADC 77 4.4 Circuit Implementation 80 4.4.1 Bootstrapped Switch 80 4.4.2 Dynamic Comparator 83 4.4.3 Digital Control Logic Circuits 85 4.4.4 Capacitive DAC Array 91 Chapter 5 Simulation and Measurement Results 93 5.1 Layout and Chip Floor Plan 93 5.2 Simulation Results 96 5.3 Grounding in PCB Design 98 5.4 Die Micrograph and Measurement Setup 100 5.5 Measurement Results 102 Chapter 6 Conclusions and Future Works 106 Bibliography 108

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