本論文為應用於Wi - Fi 7之5.5 GHz鎖相迴路設計，內容分為兩個部份：第一部分為鎖相迴路的其中一個子電路-壓控振盪器的設計；第二部份為完整的整數型鎖相迴路設計。本論文所設計之電路皆採用TSMC 0.18 μm CMOS製程實作。
第一部分為使用可切換式電容陣列設計之D類壓控振盪器。利用D類操作的方式將交叉耦合對電晶體的尺寸加大，使其如理想開關般操作，進而達到優異的功率效率及良好的相位雜訊表現。且加入了可切換式電容陣列來進一步拓展調頻範圍。本電路量測之頻率範圍為4.93 GHz ~ 5.5 GHz，Tuning Range約為11%；相位雜訊部份在1 MHz Offset處量測時約為 - 116 dBc/Hz；輸出功率約為 - 8 dBm；功率消耗約為2.94 mW；整體晶片面積約為0.567 mm2。
第二部份為5.5 GHz整數型鎖相迴路設計。子電路包含相位頻率偵測器( PFD )、電荷幫浦( Charge Pump )、低通濾波器( Low Pass Filter )、D類壓控振盪器( Class - D VCO )以及除頻器( Divider )。整數型鎖相迴路結構簡單且易於設計與實現，適合合成穩定且固定的頻率訊號，在5.5 GHz的高頻應用下是較好的選擇。本次設計參考頻率為85.9375 MHz，輸出頻率為5.5 GHz，除頻器除數為64。在量測時根據不同參考頻率的變化可以鎖定在5.395 GHz ~ 5.6 GHz。相位雜訊量測在1 MHz Offset處約為 - 90 dBc/Hz；輸出功率皆大於 - 9 dBm；核心電路功耗約為11.6 mW；整體晶片面積約為0.754 mm2。

A 5.5 GHz phase - locked loop (PLL) for Wi - Fi 7 is presented in this thesis. It consists of two parts: the first part is the design of a class - D voltage - controlled oscillator, which is one of the sub - circuits of the phase - locked loop, and the second part is the design of a complete integer - N phase - locked loop. The VCO and PLL in this thesis were both fabricated with TSMC 0.18 μm CMOS process.
The class - D VCO is designed with a switched capactor array (SCA). By using Class D operation, the size of the cross - coupled pair transistor is increased to operate like an ideal switch to achieve excellent power efficiency and good phase noise performance. The measured frequency range is from 4.93 GHz to 5.5 GHz with a tuning range of 11%; the phase noise is about - 116 dBc/Hz at 1 MHz offset; the output power is about - 8 dBm; and the power consumption is 2.94 mW; The overall chip area is about 0.567 mm2.
The second part is a 5.5 GHz integer - N phase - locked loop design. The sub - circuits include a phase frequency detector (PFD), a charge pump (CP), a low pass filter (LPF), a class - D voltage - controlled oscillator (VCO) and a divider. The integer - N phase-locked loop is simple and easy to design and implement, which is suitable for synthesising stable and fixed frequency signals and is a better choice for high frequency applications like 5.5 GHz. The reference frequency is 85.9375 MHz, the output frequency is 5.5 GHz, and the divide ratio is 64. The output frequency of the PLL can be locked at 5.395 GHz ~ 5.6 GHz according to the variation of the reference frequency in the measurement, and the phase noise is measured to be - 90 dBc/Hz at 1 MHz offset, and the output power is greater than - 9 dBm. The power consumption of the core circuit is 11.6 mW, and the overall chip area is about 0.754 mm2 .

[1]E. Reshef, S. Vituri, and A. Gurevitz, "Wi-Fi 7 – Technology Realities and Way Forward," in IEEE International Conference on Microwaves, Communications, Antennas, Biomedical Engineering and Electronic Systems (COMCAS), pp. 1-5, July 2024
[2]R. Bhilave. "WiFi 7 Vs WiFi 6. More Speed & Capacity."
[3]T.-L. Corporation. "Wi-Fi 7 新技術:16×16 MU-MIMO."
[4]J. Park, D. Kim, R. Jo, J. Jo, Y. Pu, and K. Lee, "Multi-band PLL for RF wireless charger at 2.4 GHz and 5.8 GHz," in International SoC Design Conference (ISOCC), pp. 39-40, Oct. 2020
[5]H. Zhang, P. Xue, and Z. Hong, "A 4.6–5.6 GHz constant KVCO low phase noise LC-VCO and an optimized automatic frequency calibrator applied in PLL frequency synthesizer," in IECON 43rd Annual Conference of the IEEE Industrial Electronics Society, pp. 8337-8342, Nov. 2017
[6]S. Bain, M. U. Huq, A. N. M. Noman, A. Saleah, and S. Bhowmik, "A 4.48-5.98 GHz Frequency Range LC VCO-Based PLL for Wireless Applications with -138.6 dBc/Hz Phase Noise Suppression at 1 MHz Offset," International Conference on Computer and Information Technology (ICCIT), pp. 1-5, Dec. 2023
[7]J. H. Tsai, S. W. Huang, and J. P. Chou, "A 5.5 GHz low-power PLL using 0.18-µm CMOS technology," IEEE Radio and Wireless Symposium (RWS), pp. 205-207, Jan. 2014
[8]S. Ikeda et al., "A 0.5-V 5.5-GHz class-C-VCO-based PLL with ultra-low-power ILFO in 65 nm CMOS," in IEEE Asian Solid State Circuits Conference (A-SSCC), pp. 357-360, Nov. 2012
[9]F. Gardner, "Charge-Pump Phase-Lock Loops," IEEE Transactions on Communications, vol. 28, no. 11, pp. 1849-1858, 1980
[10]T. H. Lin, C. L. Ti, and Y. H. Liu, "Dynamic Current-Matching Charge Pump and Gated-Offset Linearization Technique for Delta-Sigma Fractional-N PLLs," IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 56, no. 5, pp. 877-885, 2009
[11]B. Razavi, "A study of phase noise in CMOS oscillators," IEEE Journal of Solid State Circuits, vol. 31, no. 3, pp. 331-343, 1996
[12]K. K. Hung, P. K. Ko, C. Hu, and Y. C. Cheng, "A unified model for the flicker noise in metal-oxide-semiconductor field-effect transistors," IEEE Transactions on Electron Devices, vol. 37, no. 3, pp. 654-665, 1990
[13]R. Sarpeshkar, T. Delbruck, and C. A. Mead, "White noise in MOS transistors and resistors," IEEE Circuits and Devices Magazine, vol. 9, no. 6, pp. 23-29, 1993
[14]B. Razavi and R. Behzad, RF microelectronics. Prentice hall New York, 2012
[15]D. B. Leeson, "A simple model of feedback oscillator noise spectrum," Proceedings of the IEEE, vol. 54, no. 2, pp. 329-330, 1966
[16]Y. Shin, T. Kim, S. Kim, S. Jang, and B. Kim, "A Low Phase Noise Fully Integrated CMOS LC VCO Using a Large Gate Length pMOS Current Source and Bias Filtering Technique for 5-GHz WLAN," International Symposium on Signals, Systems and Electronics, pp. 521-524, Aug. 2007
[17]J. J. Rael and A. A. Abidi, "Physical processes of phase noise in differential LC oscillators," in Proceedings of the IEEE 2000 Custom Integrated Circuits Conference (Cat. No.00CH37044), pp. 569-572, May 2000
[18]J. Kim, B. S. Leibowitz, and M. Jeeradit, "Impulse sensitivity function analysis of periodic circuits," in IEEE/ACM International Conference on Computer-Aided Design, pp. 386-391, Nov. 2008
[19]L. Fanori and P. Andreani, "Class-D CMOS Oscillators," IEEE Journal of Solid-State Circuits, vol. 48, no. 12, pp. 3105-3119, May 2013
[20]K. Okada, Y. Nomiyama, R. Murakami, and A. Matsuzawa, "A 0.114-mW dual conduction class-C CMOS VCO with 0.2-V power supply," in Symposium on VLSI Circuits, pp. 228-229, June 2009
[21]A. Mazzanti and P. Andreani, "Class-C Harmonic CMOS VCOs, With a General Result on Phase Noise," IEEE Journal of Solid-State Circuits, vol. 43, no. 12, pp. 2716-2729, 2008
[22]G. Li, L. Liu, Y. Tang, and E. Afshari, "A Low-Phase-Noise Wide-Tuning-Range Oscillator Based on Resonant Mode Switching," IEEE Journal of Solid-State Circuits, vol. 47, no. 6, pp. 1295-1308, 2012
[23]A. Bevilacqua, F. P. Pavan, C. Sandner, A. Gerosa, and A. Neviani, "Transformer Based Dual-Mode Voltage-Controlled Oscillators," IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 54, no. 4, pp. 293-297, 2007
[24]A. Bevilacqua, F. P. Pavan, C. Sandner, A. Gerosa, and A. Neviani, "A 3.4-7 GHz Transformer-Based Dual-mode Wideband VCO," in Proceedings of the 32nd European Solid-State Circuits Conference, pp. 440-443, Sept. 2006
[25]L. Fanori and P. Andreani, "A 2.5-to-3.3GHz CMOS Class-D VCO," in IEEE International Solid-State Circuits Conference Digest of Technical Papers, pp. 346- 347, Feb. 2013
[26]J. Y. Hsieh and K. Y. Lin, "A 0.7-mW LC Voltage-Controlled Oscillator Leveraging Switched Biasing Technique for Low Phase Noise," IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 66, no. 8, pp. 1307-1310, 2019
[27]L. Fanori, A. Liscidini, and P. Andreani, "A 6.7-to-9.2GHz 55nm CMOS hybrid Class-B/Class-C cellular TX VCO," in IEEE International Solid-State Circuits Conference, pp. 354-356, Feb. 2012
[28]A. Liscidini, L. Fanori, P. Andreani, and R. Castello, "A 36mW/9mW power-scalable DCO in 55nm CMOS for GSM/WCDMA frequency synthesizers," in IEEE International Solid-State Circuits Conference, pp. 348-350, Feb. 2012
[29]B. Razavi, Design of Analog CMOS Integrated Circuits. 2000
[30]C. Barrett. "Fractional/Integer-N PLL Basics."
[31]T. A. D. Riley, M. A. Copeland, and T. A. Kwasniewski, "Delta-sigma modulation in fractional-N frequency synthesis," IEEE Journal of Solid-State Circuits, vol. 28, no. 5, pp. 553-559, 1993
[32]B. Razavi, Design of CMOS Phase-Locked Loops: From Circuit Level to Architecture Level. 2020
[33]K. Kundert, Predicting the Phase Noise and Jitter of PLL-Based Frequency Synthesizers. 2015
[34]M. Apostolidou, Baltus, P. G. M., & Vaucher, "Phase noise in frequency divider circuits," 2008
[35]W. H. Chen, M. E. Inerowicz, and B. Jung, "Phase Frequency Detector With Minimal Blind Zone for Fast Frequency Acquisition," IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 57, no. 12, pp. 936-940, 2010
[36]C. Eichenberger and W. Guggenbuhl, "On charge injection in analog MOS switches and dummy switch compensation techniques," IEEE Transactions on Circuits and Systems, vol. 37, no. 2, pp. 256-264, 1990
[37]M. Dixit, S. C. Shrivastava, and P. Dixit, "A 5–5.47GHz LC-VCO using varactor configuration in 0.18um CMOS technology," in International Conference on Signal Processing and Integrated Networks (SPIN), pp. 887-890, Feb. 2015
[38]P. Kumar, E. Böhme, J. Al-Eryani, P. P. Bora, D. Borggreve, and L. Maurer, "A 300 mV, low power VCO with the central Frequency of 4.89 GHz in 22 nm FDSOI," in IEEE Asia-Pacific Microwave Conference (APMC), pp. 1378-1380, Dec. 2019
[39]B. E. Seow, M. H. Lin, T. H. Huang, and H. R. Chuang, "5-GHz gm-boosted transformer cross-coupled current-reused colpitts VCO," in IEEE International Symposium on Radio-Frequency Integration Technology (RFIT), pp. 1-3, Aug. 2016
[40]C. C. Lim, H. Ramiah, J. Yin, N. Kumar, P. I. Mak, and R. P. Martins, "A 5.1-to-7.3 mW, 2.4-to-5 GHz Class-C Mode-Switching Single-Ended-Complementary VCO Achieving >190 dBc/Hz FoM," IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 66, no. 2, pp. 237-241, 2019
[41]W. Wu et al., "A 5.5-7.3 GHz Analog Fractional-N Sampling PLL in 28-nm CMOS with 75 fsrmsJitter and −249.7 dB FoM," in IEEE Radio Frequency Integrated Circuits Symposium (RFIC), pp. 6403-6408, June 2018
[42]D. Liao and F. F. Dai, "A Fractional-N Reference Sampling PLL With Linear Sampler and CDAC Based Fractional Spur Cancellation," IEEE Journal of Solid-State Circuits, vol. 56, no. 3, pp. 694-704, 2021
[43]A. T. Narayanan et al., "A fractional-N sub-sampling PLL using a pipelined phase-interpolator with a FoM of −246dB," in ESSCIRC Conference European Solid-State Circuits Conference (ESSCIRC), pp. 380-383, Sept. 2015
[44]S. Ikeda, S. Lee, H. Ito, N. Ishihara, and K. Masu, "A 0.5 V 5.96-GHz PLL With Amplitude-Regulated Current-Reuse VCO," IEEE Microwave and Wireless Components Letters, vol. 27, no. 3, pp. 302-304, 2017