隨著人工智慧與記憶體的快速發展，傳統的馮紐曼計算機架構因需要大量的資料搬移，發展受到了阻礙。擁有非揮發特性的鐵電記憶體，被用來當作記憶體內運算與類神經網路運算權重儲存的媒介，因其高存取速度、優異的可靠性、低功耗等特性，有望成為新一代記憶體的首選。
本研究使用氮氧化鋁介面層搭配晶種層與氧化鉿鋯當作閘極的堆疊方式，分別製作了「先退火後蝕刻（圖形化）」與「先蝕刻（圖形化）後退火」的鐵電電容，並對電容進行了 GIXRD、XPS 材料分析與 PUND 電性測試，調整製程的順序以決定最佳的退火時機，確保在製程上能發揮最大鐵電效益。以此閘極堆疊製作的鰭式場效電晶體，在不考慮量子效應的前提下，可以達成等效氧化層厚度接近 1 奈米的超薄鐵電層。
研究結果顯示：在同樣使用晶種層的情況下，使用氮氧化鋁介面層相較於二氧化矽可以獲得較大記憶視窗與較低的次臨界擺幅。此外，本研究探討了合成氣體退火是否能進一步提升使用氮氧化鋁介面層之電晶體的性能，並證實了新興介面層應用在鐵電記憶體微縮的潛力，以及在去極化效應的限制下利用極薄的鐵電薄膜產生良好的鐵電性能，以提高鐵電記憶體在非揮發性記憶體的優勢。最後，透過片不同長度的測試架構對電阻的萃取，進而計算出通道電阻，作為評估電晶體開啟時的電流是否受到限制的依據。

With the rapid development of artificial intelligence and memory, the conventional Von Neumann computer architecture has been hindered by the requirement for massive data transfer. Non-volatile ferroelectric memory, utilized as a medium for in-memory computing and weight storage in neural network computation, is expected to become the premier choice for next-generation memory due to its characteristics such as high access speed, excellent reliability, and low power consumption.
In this study, ferroelectric capacitors were fabricated using a gate stack configuration consisting of an AlON interfacial layer combined with a seed layer and HZO, evaluating both annealing-first (followed by etching) and etching-first (followed by annealing) schemes. Material characterizations including GIXRD and XPS, along with PUND electrical testing, were conducted on the capacitors to adjust the fabrication sequence and determine the optimal annealing timing, ensuring the maximization of ferroelectric efficiency during processing. The FinFETs fabricated with this gate stack can achieve an ultra-thin ferroelectric layer with an EOT approaching 1 nm, under the premise of neglecting quantum effects.
Experimental results demonstrate that, under the identical implementation of the seed layer, the utilization of the AlON interfacial layer yields a larger memory window and a lower subthreshold swing (SS) compared to SiO2. Furthermore, this study investigated whether forming gas annealing (FGA) can further enhance the performance of transistors with the AlON interfacial layer, confirming the scaling potential of this emerging interfacial layer in ferroelectric memory, as well as the capability to achieve robust ferroelectric performance using an ultra-thin ferroelectric film under the constraints of the depolarization effect, thereby strengthening the advantages of ferroelectric memory in non-volatile memory applications. Finally, through the extraction of resistance using test structures of different lengths, the channel resistance was calculated to serve as a basis for evaluating whether the ON-state current of the transistor is restricted.

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