算術單元為數位系統中進行基本運算最主要的部份，特別是在計算機微處理器以及數位訊號處理器。本論中我們提出一個可重置浮點輔助運算單元架構，比傳統的整數和浮點架構更具有彈性及高性能。此架構可以處理8位元、16位元、32位元有符號/無符號的整數乘法運算，也可處理8位元、16位元、32位元和64位元加/減的加法運算。在浮點運算中，能夠處理IEEE浮點數標準格式的加/減/乘運算。在整數運算中，我們利用“單指令多資料指令集” (SIMD)技術，來同時處理大量較低位元寬度的運算。我們所提出的可重置架構，可做為輔助運算處理器單元或一般用途處理器的架構單元。實驗的結果顯示我們所提出的可重置架構，最大操作頻率可達309MHz。

Arithmetic units are the main components of digital systems for performing the fundamental operations of arithmetic, especially for microprocessors and digital signal processors. In this thesis, we propose a reconfigurable floating-point co-processor unit architecture that has higher performance and flexible than the traditional integer and floating-point arithmetic unit. It can perform 8-bit, 16-bit, 24-bit and 32-bit signed/unsigned integer multiplication, and perform 8-bit, 16-bit, 32-bit and 64-bit add/sub adder. For floating-point operations, it can perform IEEE standard single precision floating-point add/sub/mul operations. For integer operations, we use “single instruction multiple data” (SIMD) technology to perform a lot of lower bit width of operands at the same operation. The proposed reconfigurable arithmetic unit can be used as a co-processing unit or an arithmetic unit in general-propose processors. The experimental result indicated that the maximum operation frequency of proposed reconfigurable
arithmetic unit is 309MHz.

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