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研究生: 黃秀祺
Huang, Hsiu-Chi
論文名稱: 基於第二型離散正弦轉換之正、逆改進型離散正餘弦轉換固定係數架構設計
DST-II Based Recursive Fixed-Coefficient and Multiplication-Free Architecture Design for Forward and Inverse MDCT/MDST Algorithms
指導教授: 羅錦興
Luo, Ching-Hsing
共同指導教授: 賴信志
Lai, Shin-Chi
學位類別: 碩士
Master
系所名稱: 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年: 2014
畢業學年度: 102
語文別: 英文
論文頁數: 123
中文關鍵詞: 改進型離散正餘弦第二型離散正弦轉換遞迴固定係數品質因子CSD乘法器
外文關鍵詞: modified discrete cosine/sine transform, DST-II, recursive, fixed-coefficient, Q factor, CSD multiplier
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  • 本論文提出兩個基於固定係數第二型離散正弦轉換架構,支援正、逆改進型離散正餘弦轉換。改進型離散餘弦轉換被使用在許多音訊編解碼器中,包括:進階音訊編碼(AAC(MPEG-4))、AC-3、ATRAC1、ATRAC3plus、CELT、MP3 (MPEG-1, 2, 2.5 Audio Layer III)、Opus (Hybrid mode)、Real Audio、Vorbis (Ogg)、Windows Media Audio Standard、和Windows Media Audio Pro等等。最近MPEG (Motion Pictures Experts Group)發表的3D編解碼器同時被稱作Unified Speech and Audio Coding (USAC),改進型離散正餘弦轉換皆被使用在其中一種complex stereo prediction。
    由於改進型離散正餘弦轉換皆可以用第四型離散正弦轉換表示,而且第四型離散正弦轉換又可以被推導成四種第二型離散正弦轉換型式,因此改進型離散正餘弦轉換可以以第二型離散正弦轉換型式呈現。這裡提出的第一個第二型遞迴離散正弦轉換架構僅需一個乘法器、三個加法器和兩個延遲來實現,且乘法器還能用CSD (Canonical Signed Digit)乘法器的方式以更少的位移器和加法器取代掉全部的乘法運算量。這裡品質因子(Q factor)被用來確保系統在最穩定的狀態。為了加速設計,因此又提出一個輸入摺疊過的第二型離散正弦轉換架構,這個架構的運算週期數為第一個的一半,運算複雜度與引用的過去文獻比較下能達到大約四分之一的運算量。
    為了使用硬體描述語言來驗證提出的第二型離散正弦轉換架構,這裡先以MATLAB確認架構中的節點和係數所需位元數,然後再在Altera 的 DSP Builder中將架構建好和調整成確認後的位元長度。跑過Signal Compiler和Testbench工具後,所提出的第二型離散正弦轉換架構即可在Quartus II 和Modelsim中被program和驗證。而所跑出的峰值信噪比(PSNR)皆超過90dB,符合音訊的規格。

    This thesis proposes a signed DST-II fixed coefficient kernel for implementing MDST and MDCT designs. MDCT is used in various audio codecs including Advanced Audio Codec (AAC (MPEG-4)), AC3, ATRAC1, ATRAC3, ATRAC3plus, CELT, MP3 (MPEG-1, 2, 2.5 Audio Layer III), Opus (Hybrid mode), Real Audio, Vorbis (Ogg), Windows Media Audio Standard, and Windows Media Audio Pro. In the recently developed 3D audio codec also known as Unified Speech and Audio Coding (USAC) by MPEG, both MDCT and MDST are used in one of the two forms of complex stereo prediction.
    Since MDCT and MDST can both be represented as a DST-IV transform, and DST-IV transform can be further derived into 4 transforms represented by DST-II, MDCT and MDST can both be realized by DST-II kernel. The Proposed DST-II structure requires only one multiplier, three adders and two delays in implementation. Additionally, the multiplier can be further replaced by fewer shifters and adders using CSD representation. A q factor is used to minimize quantization effect.
    To verify the DST-II kernel running in hardware description language, the node and coefficient bits required for the kernel are configured by MATLAB, and the structure of the kernel with configured word length is built in Altera’s DSP Builder. By running the Signal Compiler and Testbench tool, the signed DST-II kernel is programmed and verified in Quartus II and Modelsim. And the PSNR of extracted output values exceeds 90dB, which is suitable for audio implementation.

    中文摘要 I Abstract III Contents V List of Tables VIII List of Figures IX Chapter 1 Introduction - 1 - 1.1 Audio Codecs using MDCT and MDST - 1 - 1.2 Motivation - 9 - 1.3 Introduction to Existing Algorithms - 11 - 1.4 Thesis Outline - 13 - Chapter 2 Existing Recursive MDCT/IMDCT、MDST/IMDST Algorithms - 14 - 2.1 Chiang et al. MDCT/IMDCT Algorithm [17] - 15 - 2.2 Nikolajevic et al. MDCT/ MDST and its Inverse Transform Algorithm [21] - 20 - 2.2.1 MDCT/MDST Algorithm Derivation - 20 - 2.2.2 IMDCT/IMDST Algorithm Derivation - 23 - 2.3 Yang et al. Adjustable Fixed Coefficient DCT Structure [29] - 26 - 2.3.1 DCT-III fixed coefficient recursive kernel - 26 - 2.3.2 DCT-IV fixed-coefficient recursive structure - 28 - 2.3.3 DCT-II Recursive Fixed Coefficient Structure - 29 - 2.4 Cheng et al. selectable fixed-coefficient recursive structure [30] - 31 - 2.5 Koening et al. MDCT/MDST/IMDCT/IMDST Algorithm [32] - 37 - 2.5.1 MDCT Algorithm Derivation - 37 - 2.5.2 MDST Algorithm Derivation - 39 - 2.5.3 IMDCT Algorithm Derivation - 40 - 2.5.4 IMDST Algorithm Derivation - 41 - Chapter 3 Fixed Coefficient Recursive Signed DST-II Algorithm for implementing MDCT/IMDCT/MDST/IMDST - 43 - 3.1 Signed DST-II Based MDCT/IMDCT/ MDST/IMDST - 43 - 3.1.1 DST-IV based MDCT [23] - 43 - 3.1.2 DST-IV Based IMDCT [23] - 47 - 3.1.3 DST-IV based MDST [34] - 52 - 3.1.4 DST-IV based IMDST [34] - 52 - 3.1.5 Signed DST-II based DST-IV [34] - 53 - 3.1.5.1 First algorithm - 56 - 3.1.5.2 Second algorithm - 57 - 3.1.5.3 Third algorithm - 58 - 3.1.5.4 Fourth algorithm - 59 - 3.2 Derivation of Proposed Fixed coefficient DST-II Structure - 60 - 3.2.1 Introduction to Fixed coefficient method - 60 - 3.2.2 Derivation of fixed coefficient signed DST-II - 62 - 3.2.3 Folded Signed DST-II Structure - 67 - 3.3 Selectable Coefficient(Q-factor) - 72 - 3.3.1 Coefficient quantization effect on IIR System [36] - 72 - 3.3.2 Hardware Architecture and the selection of Q-factor - 76 - 3.3.3 Q-factor calculation for Stabilizing Fixed Coefficient Signed DST-II Structure - 77 - 3.3.3.1 Q-factor for first proposed structure: - 77 - 3.3.3.2 Q-factor for second proposed structure : - 80 - 3.4 CSD Implementation and Word Length Determination - 86 - Chapter 4 Signed DST-II Structure Verification - 91 - 4.1 Introduction to Altera’s DSP Builder - 91 - 4.2 Verification of Signed-DST-II Structure and Folded Structure - 92 - 4.2.1 DSP Builder Simulation Flow and Results - 92 - Chapter 5 Comparison with Existing Algorithms - 104 - 5.1 Required Computational Cycle Evaluation and Comparison - 104 - 5.1.1 Arithmetic Computational Cycle Comparison for MDCT/MDST - 105 - 5.1.2 Computational Complexity Comparison for IMDCT/IMDST - 106 - 5.2 Analysis of Computational Complexity - 107 - 5.2.1 Computational Complexity Analysis for MDCT/MDST - 108 - 5.2.2 Computational Complexity Analysis for IMDCT/IMDST - 109 - 5.2.3 Computational Complexity regarding the use of CSD Multiplier - 110 - 5.3 Hardware Cost and Required Coefficient Comparison - 112 - 5.4 PSNR accuracy analysis - 115 - Chapter 6 Conclusion - 118 - References - 119 -

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