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研究生： 劉昀儒
Liu, Yun-Ju
論文名稱： 一個應用於S/PDIF音效處裡的時脈與資料回復電路
A Clock and Data Recovery for S/PDIF Audio Application
指導教授： 郭泰豪
Kuo, Tai-Haur
學位類別： 碩士
Master
系所名稱： 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年： 2004
畢業學年度： 92
語文別： 英文
論文頁數： 78
中文關鍵詞： 時脈與資料回復電路
外文關鍵詞： Clock and Data Recovery, CDR
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    • 本篇論文是實現一個S/PDIF的數位音效接收器，內建一個用0.35微米雙多晶層四金屬層的CMOS製程的時脈與資料回復電路（簡稱CDR）。本電路根據S/PDIF的介面標準來對音效與數位資料做接收和粹取時脈的工作。晶片中包含線接收器和一個時脈與資料回復電路，具有回復時脈與同步信號的功能和多路傳輸音效與數位資料的能力。

    此晶片的主要功能是回復音效資料並從數位的傳輸線中取得且產生低污染的時脈。從時脈與資料回復電路所產生的時脈有主時脈（MCK，256倍的取樣頻率），信號時脈（SCK，64倍的取樣頻率）和基礎頻率（FSYNC，1倍或2倍的取樣頻率）。被接收的音效資料（S/PDIF）能利用數位解碼器來轉換成I2S的音效格式。因此，本篇論文實現了一個S/PDIF的數位音效接收器，內建一個用時脈與資料回復電路。在一些應用方面像是接在光碟機輸出端的音效接收器或是接在數位電視輸出端的音效接收器，等等。

    整個IC晶片的總面積是0.657mm2而其中不含Pads的總面積是 0.249mm2。此晶片的總功率消耗是33.5mW。

    A S/PDIF Digital Audio Receiver with an Internal Clock and Data Recovery (CDR) circuit is implemented in 0.35um 2P4M CMOS Technology. The circuit receives audio and digital data according to the S/PDIF interface standard. The chip contains line receivers and a clock and data recovery circuit that recovers the clock and synchronization signals, and de-multiplex audio and digital data.

    The primary function of the chip is to recover audio data and low jitter clocks from a digital transmission line. The clocks that can be generated by CDR are MCK (256x Fs), SCK (64x Fs), and FSYNC (Fs or 2x Fs). The recovered audio data (S/PDIF) can be transferred into I2S format by digital decoder. Thus, this thesis implements a S/PDIF Digital Audio Receiver with an Internal clock and data recovery circuit. Applications such as CD-ROM output audio receiver, Digital TV output audio receiver, etc..

    The chip total area is 0.657mm2 and active area is 0.249mm2. The total power consumption is 33.5mW.

    Contents 1 Introduction 1 1.1 Background ………………………………………… 1 1.2 Motivation ………………………………………… 2 1.3 Thesis Organization ……………………………… 3 2 Audio Systems 5 2.1 Introduction ……………………………………… 5 2.2 Audio Data Format ………………………………… 6 2.2.1 Bi-Phase Mark Coding ………………………… 9 2.2.2 I2S, Right Alignment, Left Alignment Format … 11 2.3 Specification for Audio Systems …………… 14 2.3.1 AES/EBU Professional Format ……………… 15 2.3.2 S/PDIF Consumer Format ……………………… 15 3 Fundamentals and Design Techniques of Clock and Data Recovery 17 3.1 General Considerations ………………………… 17 3.2 Phase Detectors for Random Data …………… 19 3.2.1 Hogge Phase Detector ……………………… 20 3.2.2 Alexander Phase Detector ………………… 22 3.2.3 Half-Rate Phase Detector ………………… 25 3.3 Frequency Detectors for Random Data ……… 30 3.4 CDR Architectures ……………………………… 33 3.4.1 Full-Rate Referenceless Architecture … 34 3.4.2 Dual-VCO Architecture …………………… 35 3.4.3 Dual-Loop Architecture with External Referenc … 37 4 Circuits implementation of Clock and Data Recovery and Digital Decoder 40 4.1 Introduction ……………………………………… 40 4.2 Design of Clock and Data Recovery ………… 41 4.2.1 Phase Detector ……………………………… 42 4.2.2 Frequency Detector ………………………… 48 4.2.3 Charge Pump and Loop Filter ……………… 49 4.2.4 Voltage-Controlled Oscillator …………… 51 4.2.4.1 Digital Logic Control Circuit ( Coarse Tune ) ……………………… 57 4.2.4.2 Replica Bias Voltage Control Circuit ( Fine Tune ) ……………… 60 4.2.5 Differential to Single-Ended Circuit …… 64 4.2.6 9-Bits Synchronous Divider ………………… 66 4.2.7 Phase-Locked Loop and Frequency-Locked Loop … 68 4.2.8 CDR Layout ……………………………………… 70 5 Verifications and Measurements 71 6 Conclusions and Future Works 73 References 75

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