隨著製程技術快速發展，整合各種功能的核心電路在一系統單晶片內已成為一種相當熱門的設計方法。但對於此種大型且複雜的設計，其低可觀察性及低可控制性將使晶片的驗證與除錯變得相當困難而極可能延誤產品的上市時間。在此情況下，系統設計者將極度需要一套有系統的除錯方法以有效縮短除錯驗證所耗費的時間。
在本論文中，我們延續先前發展之具有硬體中斷點功能的單晶片系統除錯平台，開發針對核心電路的事件觸發及即時修改等除錯功能。我們所提供的事件觸發功能具有高度彈性，可讓系統設計者以相當簡單的方式設定硬體中斷點。除此之外，當系統單晶片執行至硬體中斷點時，使用者除了可藉由內建除錯電路獲得電路內部之詳細資訊外，更能透過即時修改機制任意修改核心電路之內部狀態以大幅提昇系統單晶片之可控制性。值得一提的是，我們盡量地重複使用系統單晶片的系統資源及原有測試元件來實現上述功能，因此只需相當少量的額外硬體。我們也針對所開發的除錯平台撰寫了一套具有使用者圖形介面之自動化系統，讓使用者可利用此套軟體控制我們所開發之除錯硬體及觀察電路資訊，有效率地解決矽晶片之除錯問題。

With the rapid development of semiconductor manufacturing technology, integrating various IP cores into a System-on-Chip (SoC) has become a quite popular manner in IC design. However, the low observability and controllability of such complex silicon chips also complicate the debugging and verification process, which may adversely increase the time to market of products.
Based on a previously developed SoC debug platform with cycle-based breakpoint insertion capability, in this thesis we add two advanced features to this platform and show that the observability and controllability of silicon chips can be greatly enhanced with these features. These two features are related to an Event Trigger facility and an Inside-Core Adjustment capability. The Event Trigger function is very flexible where users can easily set hardware break points. The Inside-Core Adjustment feature, on other the other hand, allows users to not only obtain detailed information of IP core, but also quickly and easily modify the inner status of the cores when SoC chips are suspended at user-defined breakpoints. It is worth to mention that we reuse the available system resources and design-for-test components as much as possible, and thus only little additional hardware is required to enable the proposed debug capabilities. We also provide a set of automation tools equipped with graphic user interface to help user control debug hardware and monitor the traced data from chips so as to efficiently address the silicon debug problems.

[1] Si-Yuan Liang and Kuen-Jong Lee, "A Low-Cost On-Chip SoC Debug Platform with Hardware Breakpoint Insertion and Single Step Capabilities for IP Cores", Master Thesis, Dept. of E.E., NCKU, Taiwan, 2008.
[2] Shao-Yuan Chen and Kuen-Jong Lee, "A Low-Cost On-Chip SOC Debug Platform with On-Line Monitor Capability for System Bus and IP Cores", Master Thesis, Dept. of E.E., NCKU, Taiwan, 2008.
[3] Ho Fai Ko, N. Nicolici, "On Automated Trigger Event Generation in Post-Silicon Validation," Proc. Design, Automation and Test in Europe, pp. 256-259, 2008.
[4] B. Vermeulen, "Functional Debug Techniques for Embedded Systems," IEEE Design & Test of Computers, vol. 25, no. 3, pp. 208-215, 2008.
[5] M.C Hsieh and C.T. Huang, "An Embedded Infrastructure of Debug and Trace Interface for DSP Platform," Proc. Design Automation Conference, pp. 866-871, 2008.
[6] Shan Tang and Qiang Xu, "A Debug Probe for Concurrently Debugging Multiple Embedded Cores and Inter-Core Transactions in NoC-Based Systems," Proc. Design Automation Conference, pp. 416-421, 2008.
[7] M. Abramovici, "In-System Silicon Validation and Debug," IEEE Design & Test of Computers, vol. 25, no. 3, pp. 216-223, 2008.
[8] Jian-Jhih You and Kuen-Jong Lee, "High-Performance Component Design for SOC Test Platforms with Mixed-Signal Test Capability," Master Thesis, Dept. of E.E., NCKU, Taiwan, 2007.
[9] Shan Tang and Qiang Xu, "A Multi-Core Debug Platform for NoC-Based Systems," Proc. Design, Automation and Test in Europe, pp. 1-6, 2007.
[10] Wen-Cheng Huang, Chin-Yao Chang and Kuen-Jong Lee, "Toward Automatic Synthesis of SOC Test Platform," Proc. VLSI Design, Automation, and Test, pp. 1-4, 2007.
[11] Yu-Chin Hsu, Furshing Tsai, Wells Jong, and Ying-Tsai Chang, "Visiblity Enhancement for Silicon Debug," Proc. Design Automation Conference, pp. 13-18, 2006.
[12] M. Abramovici, P. Bradley, K. Dwaeakanah, P. Levin, G. Memmi and D. Miller, "A Reconfigurable Design-for-Debug Infrastructure for SOCs," Proc. Design Automation Conference, pp. 7-12, 2006.
[13] Kuen-Jong Lee, Chia-Yi Chu, and Yu-Ting Hong, "An Embedded Processor Based SOC Test Platform," Proc. Int'l Symp. on Circuits and Systems, pp. 2983-2986, 2005.
[14] Wilco de Boer, Bart Vermeulen, "Silicon Debug: Avoid Needless Respins," Proc. Int'l Electronics Manufacturing Technology Symposium, pp. 277-281, 2004.
[15] B. Vermeulen, M.Z. Urfianto, and S.K. Goel, "Automatic Generation of Breakpoint Hardware for Silicon Debug," Proc. Design Automation Conference, pp. 514-517, 2004.
[16] B. Vermeulen, S. Kumar Goel, "Design for Debug: Caching Design Errors in Digital Chips," IEEE Design & Test of Computers, vol. 19, no. 3, pp. 35-43, 2002.
[17] B. Vermeulen et al., "IEEE 1149.1-Compliant Access Architecture for Multiple Core Debug on Digital System Chips," Proc. IEEE Int'l Test Conf., pp. 55-63, 2002.
[18] B. Vermeulen et al., "Core-Based Scan Architecture for Silicon Debug," Proc. IEEE Int'l Test Conf., pp. 638-647, 2002.
[19] Yu-Ting Hong and Kuen-Jong Lee, "An Embedded-Processor-Driven Platform for SOC Testing," Master Thesis, Dept. of E.E., NCKU, Taiwan, 2002.
[20] AMBA Specification, http://www.arm.com
[21] IEEE 1500 Standard, http://grouper.ieee.org/groups/1500/
[22] GTK+ Toolkit, http://www.gtk.org/