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研究生： 陳柏誌
Chen, Po-Chih
論文名稱： 低溫操作下之絕緣層上矽閘極環繞式電晶體設計以優化靜態隨機存取記憶體與環形震盪器
Silicon-On-Insulator Gate-All-Around Transistor Designs for the Optimization of SRAM and Ring Oscillator in Cryogenic Operating Temperature
指導教授： 江孟學
Chiang, Meng-Hsueh
學位類別： 碩士
Master
系所名稱： 電機資訊學院 - 奈米積體電路工程碩士博士學位學程
MS Degree/Ph.D. Program on Nano-Integrated-Circuit Engineering
論文出版年： 2023
畢業學年度： 111
語文別： 英文
論文頁數： 131
中文關鍵詞： 絕緣體上矽閘極環繞式電晶體 、6T靜態隨機存取記憶體 、讀寫穩定度 、讀寫存取速度 、低溫 、操作頻率 、功率消耗 、環形震盪器
外文關鍵詞： SOI GAAFET, 6T SRAM, read/write stability, read/write access speed, cryogenic temperature, operating frequency, power consumption, ring oscillator
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    • 根據摩爾定律，預測半導體晶片上的電晶體數量每18個月會增加一倍，隨著不同節點之間電晶體尺寸的微縮，造成元件達到物理極限，因此本篇論文探討在IRDS 2022 roadmap(G40M16/T2)2nm製程節點下，比較塊狀鰭式場效電晶體(Bulk FinFET)、絕緣層上矽鰭式場效電效晶體(SOI FinFET)、絕緣層上矽閘極環繞式電晶體(SOI GAAFET)，應用在數位電路上的優勢，並且分別從高密度和高性能的設計，在6T靜態隨機存取記憶體(6T SRAM)佈局面積上比較讀寫穩定度以及讀寫存取速度，藉由GAAFET在製程上元件佈局寬度(footprint)比起FinFET可以彈性調整的優勢，設計6T SRAM電路在高效能面積下，PU : PG : PD = 1 : α : 2，固定PU電晶體和PD電晶體 footprint為1 : 2，藉由設計PG電晶體footprint以取得讀取靜態雜訊邊界(RSNM)及寫入靜態雜訊邊界(WSNM)平衡，而由於bulk FinFET在設計上PG只能以整數調整(α = 1 或 2)，因此在讀取及寫入的抗雜訊能力無法精準匹配。
    本篇論文同時比較元件操作在室溫(T = 300K)以及低溫(T = 77K)下，分析元件在不同操作電壓(Vdd)下的讀寫穩定度以及讀寫速度，最後藉由TCAD mixed-mode元件/電路模擬實現環形震盪器電路模擬，分別討論對於不同元件以及不同溫度下，元件的操作頻率以及功率消耗上的特性分析。

    According to Moore's Law, the number of transistors on semiconductor chips is predicted to double every 18 months. However, as the transistor sizes shrink with different nodes, the devices are approaching their physical limits. Therefore, this paper investigates the advantages of bulk FinFET, SOI FinFET, and SOI GAAFET for digital circuit applications at the 2 nm process node based on the IRDS 2022 roadmap (G40M16/T2).It focuses on both High-Density and High-Performance designs and compares the read/write stability, and read/write access speed in a 6T SRAM layout.
    By leveraging the flexibility of GAAFETs in adjusting the footprint (device layout width) compared to FinFETs, the design of the 6T SRAM circuit in the High-Performance mode adopts a PU : PG : PD ratio of 1 : α : 2, with fixed PU transistor and PD transistor footprints of 1 : 2. The PG transistor footprint is optimized to achieve a balance between RSNM and WSNM, which is challenging for bulk FinFETs as their PG transistor can only be adjusted as an integer (α = 1 or 2). Therefore, the anti-noise capability of read and write operations cannot be precisely matched.This paper also compares the performance of the devices at room temperature (T = 300K) and cryogenic temperature (T = 77K), analyzing the read stability and write stability, as well as the access speed at different operating voltages (Vdd). Finally, TCAD mixed-mode device/circuit simulations are performed to evaluate the characteristics of operating frequency and power consumption for different devices and temperatures using ring oscillator circuits.

    摘要 I Abstract III 誌謝 IV Contents VI Table Captions IX Figure Captions XIII Chapter 1 Introduction 1 1.1 Background 1 1.2 Motivation 2 1.3 The framework of the thesis 5 Chapter 2 Evolution of Advanced Devices and Semiconductor Characteristics at Cryogenic Temperature 7 2.1 The evolution of advanced transistors 7 2.2 Semiconductor Characteristics at Cryogenic Temperature 10 2.2.1 Band Tails 10 2.2.2 Mobility Enhancement 12 2.2.3 Steep Subthreshold Swing 15 Chapter 3 Key Metrics on SRAM Stability and Read/Write Access Speed 18 3.1 Introduction of 6T SRAM 18 3.2 6T SRAM Bitcell Architecture 18 3.3 Hold Operation 21 3.4 Read Operation 23 3.4.1 Read Static Noise Margin (RSNM) Measurement 26 3.5 Write Operation 27 3.5.1 Write Static Noise Margin (WSNM) Measurement 30 3.6 Current-Voltage Relationship (N-Curve) 31 3.7 SRAM Size Trade-off in Design 35 Chapter 4 Comparison of Intrinsic Delay and Performance of Bulk FinFETs, SOI FinFETs and SOI NSFETs in Different Footprint Designs 37 4.1 The Physical Models Used for TCAD Simulations 37 4.1.1 Fermi, Temperature, and Effective Intrinsic Density 37 4.1.2 Mobility 38 4.1.3 Band Tails 42 4.1.4 Recombination 43 4.1.5 Improving Convergence Issues in TCAD 44 4.2 High-Performance Device Structure 45 4.3 Basic Definition of Transfer Characteristics 51 4.4 Analysis of The Electrical Characteristics of Different Devices 53 4.5 Advantages of SOI GAAFETs for High-Density and High-Performance Applications 55 Chapter 5 Comparison of The Bulk FinFETs and SOI NSFETs Characteristic on 6T SRAM in High-Performance Layout Design 60 5.1 Bulk FinFETs and SOI NSFETs in High-Performance Layout Designs 60 5.2 Optimized PG Transistor Footprint Design for SRAM Read and Write Stability 64 5.3 PG Transistor Design for SRAM Read/Write Access Speed Optimization 67 Chapter 6 Comparison of The Bulk FinFETs and SOI NWFETs Characteristic on 6T SRAM at Room Temperature and Cryogenic Temperature respectively in High-Density Layout Design 70 6.1 Bulk FinFETs and SOI NWFETs in High-Density Layout Design 70 6.2 High-Density Device Structure 72 6.3 Comparison of SRAM Stability and Access Speed at Room Temperature 74 6.4 Low Power SRAM Design at Cryogenic Temperature 81 Chapter 7 Comparison of The Bulk FinFETs and SOI NWFETs Characteristic on 6T SRAM at Room Temperature and Cryogenic Temperature respectively in High-Density Layout Design 97 7.1 Measurement of Power Consumption and Frequency 97 7.2 Comparison of PPA between Bulk FinFETs and SOI NWFETs at Room Temperature 100 7.3 Comparison of PPA between Bulk FinFETs and SOI NWFETs at Cryogenic Temperature 109 7.4 Comparison of Devices PPA under The Same DC Conditions 118 Chapter 8 Conclusion 123 Future work 125 Appendix 126 Accepted IEEE Conference Paper 127 References 127

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