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研究生：	劉建宏 Liu, Jian-Hong
論文名稱：	異質性多處理器嵌入式系統微核心之設計與實作 A Micro-Kernel for Embedded Systems with Heterogeneous Multiprocessors
指導教授：	陳　敬 Chen, Jing
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 電機工程學系 Department of Electrical Engineering
論文出版年：	2004
畢業學年度：	92
語文別：	中文
論文頁數：	54
中文關鍵詞：	異質性多處理器、嵌入式系統、微核心
外文關鍵詞：	heterogeneous multiprocessors, microkernel, embedded systems
相關次數：	點閱：110 下載：3
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　　本篇論文採用微核心架構在異質性多處理器上建構核心，經由在不同處理器上執行相同設計之核心以提供上層應用程式統一的介面。上層應用程式可依據其所在處理器的特性執行相對應的服務等待其它應用程式的請求。藉由在不同處理器上執行相同核心以及不同特性的應用程式達到系統的擴充性以及彈性。
　　本文主要在闡述說明異質性多處理器上微核心的設計。本論文所設計的微核心是以訊息傳遞為基礎；並且將核心分成四個主要部份：行程間通訊、硬體中斷處理、處理器間通訊與排程器。行程間通訊負責行程間的訊息傳遞；發生硬體中斷時則交由硬體中斷處理；處理器間欲相互溝通則是交由處理器間通訊處理；排程器依排程策略負責選出下一個將執行的行程。
　　本文所使用的實作平台為德儀公司(Texas Instruments) TMS320DSC25。其內包含了ARM7TDMI與C5409兩個微處理器核心、週邊控制等，屬於異質性多處理器的系統晶片。ARM7是一通用型的32位元處理器可用來控制所有的週邊控制，例如：串列埠、記憶卡、螢幕顯示等週邊輸入輸出裝置。C5409則是一16位元訊數位號處理器，其主要功能是在數位訊號處理上有顯著的效能。
藉由在DSC25上執行本文設計之微核心，在不同處理器上執行之行程可利用本核心所設計之處理器間通訊傳遞訊息、要求服務以完成特定工作。經由測量本核心在TSM320DSC25上執行之時間可以得到：無論是在那一個處理器上執行本核心，核心內每個關鍵區域之執行時間皆為可預測性。

　　This thesis presents how to build a kernel which is based on micro-kernel architecture on a SOC of heterogeneous multiprocessors. The micro-kernel architecture is based on message-passing mechanism. There are four essential parts in the kernel, namely inter-process communication, hardware interrupt handler, inter-processor communication and scheduler. Message-passing between processes is the responsibility of inter-process communication. When a hardware interrupt is triggered, hardware interrupt handler must handle it. Inter-processor communication handles the communication between processors. Choosing next process to execute is scheduler’s duty.
　　The kernel described in this thesis has been implemented on a reference design of TI TMS320DSC25 which is a heterogeneous multiprocessors SOC containing a ARM7TDMI core and a C5409 DSP core. ARM7 is a general purpose processor with 32-bit capability, while C5409 is a digital signal processor with 16-bit capability. The ARM processor and the DSP processor run their own copy of the kernel independently. Except the hardware dependent functionality, the two copies of the kernel are designed with the same structure providing same service functions through the same application program interfaces.
　　By executing micro-kernel on DSC25, different processes executing on different processors can communicate or request services via inter-processor communication. Finally, every critical sections of the kernel, no matter whichever processor it running on, can complete in a bounded time.

第一章 簡介............................................... 1
1 背景知識.............................................. 1
1.1 多處理器架構........................................ 1
1.2 多處理器作業系統.................................... 4
2 異質性多處理器........................................ 6
3 研究動機.............................................. 7
4 章節規劃.............................................. 8
第二章 相關研究........................................... 9
1 微核心................................................ 9
1.1 微核心定義.......................................... 9
1.2 微核心架構.......................................... 9
2 異質性多處理器作業系統............................... 10
3 實例探討............................................. 12
3.1 QNX.................................................12
3.2 DSPLinux............................................13
3.3 AsyMOS..............................................15
第三章 核心架構.......................................... 17
1 硬體模式............................................. 17
2 核心總覽............................................. 18
3 行程間通訊........................................... 19
3.1 行程溝通介面....................................... 20
3.2 行程訊息傳輸方式................................... 20
3.3 訊息格式........................................... 21
4 硬體中斷............................................. 22
5 處理器間溝通介面..................................... 22
6 行程排程............................................. 24
第四章 核心實作.......................................... 25
1 硬體架構............................................. 25
1.1 DSC25 上ARM 和DSP 溝通的機制....................... 26
2 核心實作............................................. 27
2.1 行程............................................... 27
2.1.1 行程初始化....................................... 30
2.1.2 本文切換......................................... 31
2.2 行程間通訊......................................... 33
2.3 中斷處理........................................... 36
2.4 處理器間通訊....................................... 37
2.5 行程排程........................................... 39
2.6 核心初始化......................................... 40
第五章 系統測試與效能分析................................ 41
1 系統測試............................................. 41
2 效能分析............................................. 44
第六章 結論與展望........................................ 49
1 結論................................................. 49
2 展望................................................. 50
參考文獻................................................. 51
自 述.................................................... 54
                                    

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校外：2004-07-20公開

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