本論文旨在設計一個操作在480百萬赫茲，可調頻寬的時脈產生器與根據延遲鎖相迴路為基礎的資料回復系統。本系統可適用在mesochronous的連接系統中。

現今有許多高速的輸入輸出系統被整合在單一晶片上，其打線腳的數目與功率消秏的預算很緊。數位電路傳導過來的切換雜訊亦變成相當嚴重的麻煩。在這次的實作裡，時脈產生器要對這些雜訊有免疫，並同時保有低時脈抖動的特點。時脈產生器採用可調頻寬的技術，用來幫助在不同的製程變動下還能維持效能。此外，簡單但有效的雜訊消除電路被設計，以減小時脈產生器中壓控振盪器之控制電壓因為供應電壓雜訊而造成的干擾。

被用來產生多個相位時脈的延遲鎖相迴路會有起始與鎖錯相位的問題。但用來實作資料回復的延遲鎖相迴路只需要解決前一個問題。利用壓控振盪器中每一級延遲時間只有壓控延遲線的一半這個事實，一個電流訊號從壓控振盪器中被鏡射到壓控延遲線裡，藉此來粗調壓控延遲線並解決起始問題。同時，壓控延遲線可被設計為擁有較小的鎖定範圍與增益。因此較小的電容即可達到足夠的頻寬以濾掉輸入的雜訊，因此許多的面積被節省了下來。

這晶片是以台積電0.35毫米2P4M、互補金氧半混合信號製程實作。總共佔用了 325x270平方毫米的面積，並在3.3伏的供應電壓下消秏了約30微瓦的功率。

The goal of this thesis is to design an adaptive-bandwidth clock generator and a DLL (Delayed Locked Loop)-based data recovery system running at 480 MHz. This system is suitable to apply to the mesochronous interconnection.

Nowadays many high-speed I/Os are integrated into a single chip, the wire count, power budget of a system can be significantly tight. The switching noise coupled from digital blocks to analog ones also has become a serious problem. In this work, the clock generator is designed to be immune to such noise while maintaining the low-jitter characteristic. The adaptive-bandwidth technique is adopted to help the clock generator to keep its performance under different process variation. Besides, simple while effective noise-canceling circuits are designed to reduce the noise coupling from the supply voltage to the voltage controlled oscillator (VCO) of the clock generator.

The DLLs designed for multi-phase clock generator have the start-up and false-lock problems. However, the DLL implemented in the data recovery only has to resole the prior one. Taking advantages of the fact that the delayed time of the delay cells in the VCO is half of those in DLL, a coarsely-tuned current, is mirrored from VCO to DLL, elegantly resolves the start-up problem without any further reset circuits. Meanwhile, the voltage controlled delayed line (VCDL) can be designed with a smaller operating range and smaller gain. Large chip area is saved due to the smaller capacitor is sufficient to achieve the same bandwidth to filter out the input noise.

The chip is implemented in a TSMC 0.35 um 2P4M CMOS mixed-mode technology. It occupies 325x270 mm2 and consumes about 30mW at 3.3 V power supply.

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