本論文針對電子式斷路器中電流閘口絕緣閘極雙極性電晶體的控制電路進行探討。為縮小控制電路體積，以達到輕巧便利之用途，同時降低控制電路延遲，提升保護電路能力，本論文選擇利用積體電路方式來進行實作。
本論文使用台積電D35積體化製程，進行控制電路積體化設計。並且對實作出來的控制電路進行量測，將其量測參數結果應用於電子式斷路器中，進行短路故障模擬測試。實驗結果顯示，當電路發生短路故障時，可有效地在63 μs內進行電路電壓判斷，並進行電流切換，使電路分離並切斷電路。論文中利用積體電路設計出電子式斷路器之控制電路，具有相當快速、穩定等諸多優點。

In this study, the electronic circuit for controlling IGBT in circuit breaker is discussed. In order to reduce the size and improve the delay time of the control circuit, the integrated circuit is chosen to realize the control circuit in this research. Meanwhile, the proposed integrated control circuit is adopted in an electronics circuit breaker.
The integrated control circuit is realized in TSMC 0.35 μm process. The fabricated circuit is measured and the measurement results are applied to the electronic circuit breaker for short-circuit fault simulation test. According to the experimental results, this research shows the circuit voltage can be judged effectively within 63 μs in short-circuit condition, and the circuit current is switched to separate the circuit and cut off the circuit. The proposed integrated control circuit has many advantages such as relatively fast, stable and adjustable overload current.

[1] 簡潔, "600-V 溝渠式絕緣閘雙極性電晶體設計、分析與短路能力探討。," 國立中央大學電機工程學系碩士論文, 2013.
[2] 陳榮祥, "受外界機械應力下功率電晶體之電性分析及可靠度研究," 國立中山大學物理研究所碩士論文, 2009.
[3] 施敏著，黃調元譯, "半導體元件物理與製造技術," 國立交通大學出版社, 2002.
[4] J.-f. H. Jun-lin Tsai , Shih-hui Chen , Jeng Gong , Ruey-hsin Liou , and Shun-liang Hsu, "High Voltage NPN-Bipolar Transistor Using P+ -Buried Layer in BiCMOS Process," vol. IEDM Tech Dig, pp 189-192, 1999.
[5] 林彥宏, "0.25 微米 BCD 製程之高電流增益 BJT 元件與 JFET 元件設計," 碩士論文，國立清華大學電子工程研究所, 2008.
[6] K. S. Oh, "Application Note 9016 Igbt Basics 1," 2001.
[7] R. S. Chokhawala, J. Catt, and B. R. Pelly, "Gate drive considerations for IGBT modules," IEEE Transactions on Industry Applications, vol. 31, no. 3, pp. 603-611, 1995.
[8] K. J. Raut, R. V. Kshirsagar, and A. C. Bhagali, "A 180 nm low power CMOS operational amplifier," in 2014 Innovative Applications of Computational Intelligence on Power, Energy and Controls with their impact on Humanity (CIPECH), 2014, pp. 341-344.
[9] D. A. Hodges, P. R. Gray, and R. W. Brodersen, "Potential of MOS technologies for analog integrated circuits," IEEE Journal of Solid-State Circuits, vol. 13, no. 3, pp. 285-294, 1978.
[10] J. E. Solomon, "The monolithic op amp: a tutorial study," IEEE Journal of Solid-State Circuits, vol. 9, no. 6, pp. 314-332, 1974.
[11] P. R. Gray and R. G. Meyer, "MOS operational amplifier design-a tutorial overview," IEEE Journal of Solid-State Circuits, vol. 17, no. 6, pp. 969-982, 1982.
[12] G. Palmisano and G. Palumbo, "A compensation strategy for two-stage CMOS opamps based on current buffer," IEEE Transactions on Circuits and Systems I: Fundamental Theory and Applications, vol. 44, no. 3, pp. 257-262, 1997.
[13] B. K. Ahuja, "An improved frequency compensation technique for CMOS operational amplifiers," IEEE Journal of Solid-State Circuits, vol. 18, no. 6, pp. 629-633, 1983.
[14] D. R. H. a. P. E. Allen, "Cmos Analog Circuit Design.," Oxford University Press, 2007.
[15] S. S. Jamuar and K. Tang Kia, "Design of low voltage operational amplifier," in 2004 IEEE International Conference on Semiconductor Electronics, 2004, p. 3 pp.
[16] 黃弘宇, "具限流保護之 IGBT 開關電路研製及應用," 碩士論文，國立成功大學電機工程學系, 2016.
[17] S. Khucharoensin and V. Kasemsuwan, "High-speed low input impedance CMOS current comparator," in Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03., 2003, vol. 1, pp. I-I.
[18] C. Lu, S. Bingxue, and L. Chun, "A high speed/power ratio continuous-time CMOS current comparator," in ICECS 2000. 7th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.00EX445), 2000, vol. 2, pp. 883-886 vol.2.
[19] L. Luh, J. Choma, and J. Draper, "A high-speed high-resolution CMOS current comparator," in ICECS'99. Proceedings of ICECS '99. 6th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.99EX357), 1999, vol. 1, pp. 303-306 vol.1.
[20] R. d. Rio-Fernandez, G. Linan-Cembrano, R. Dominguez-Castro, and A. Rodriguez-Vazquez, "A mismatch-insensitive high-accuracy high-speed continuous-time current comparator in low voltage CMOS," in 1997 2nd IEEE-CAS Region 8 Workshop on Analog and Mixed IC Design, 1997, pp. 111-116.
[21] M. Bracey and W. Redman-White, "Design considerations for current domain regenerative comparators," in 1994 Second International Conference on Advanced A-D and D-A Conversion Techniques and their Applications, 1994, pp. 65-70.
[22] 李奕廷, "具低漣波輸出電壓之降壓型直流-直流轉換器," 碩士論文，國立成功大學電機工程學系碩博士班, 2009.
[23] I. T. AG, "TRENCHSTOPTM Series," IKW75N60T Datasheet, 2013.