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研究生： 朱宏明
Chu, Hong-Ming
論文名稱： CMOS/PTL混合式合成之二元決策圖分解
BDD decomposition for mixed CMOS/PTL synthesis
指導教授： 賴源泰
Lai, Yen-Tai
學位類別： 碩士
Master
系所名稱： 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年： 2004
畢業學年度： 92
語文別： 英文
論文頁數： 60
中文關鍵詞： 金氧化半導體 、細胞元件庫 、分解 、二元決策圖 、合成 、傳輸電晶體
外文關鍵詞： decomposition, BDD, cell library, CMOS, PTL, synthesis
相關次數： 點閱：95  下載：1 
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    • 　　本論文中，我們提出了一個新的電路合成演算法以及製作了一個新的細胞元件庫(cell library)，首先針對用BDD合成的LEAP cell做一些電路上的修正，使它能更快速更節省功率而不至於浪費面積，接著我們發現由於各種函數的特性不同，應該要使用不同的架構方法來做合成以達到效能的最佳化，於是我們在BDD的架構上去找出一些適合用傳統CMOS合成方法的函數，再把它們以一個點(node)表示然後代回原本的BDD架構，而這些以一個點所表示的函數，我把它輸出成verilog code給CMOS 電路做合成，等到BDD架構以LEAP cell合成完畢後，再把這些電路組合起來，經實驗證實，用我們所提出的合成方法以及新的LEAP cell比起傳統的CMOS合成方法來的更快速，節省空間以及功率的消耗。

    　　In this paper, we propose a new synthesis algorithm and a new cell library. At first, we modify the LEAP cell and call it as new LEAP cell. The new LEAP cell contains nY cells and cY cells. They have higher speed, lower power, and less area than the old ones. Logic functions have two kinds of characteristics: unite and binate. Based on these two characteristics, we use different logic styles to mapping logic functions. Hence, we find the functions in a BDD which are suitable for CMOS mapping. Then, replace the BDD of this function to a node and mapping to CMOS. Finally, we compose circuits which are mapping to PTL and static CMOS. The Experimental Results show that our approach has better performance and less area than conventional CMOS technology mapping.

    Chapter 1 Introduction.........................................1 1.1 Binary Decision Diagrams(BDDs).......................................2 1.2 Ordered Binary Decision Diagrams (OBDDs)..............................................4 1.3 Reduced Ordered Binary Decision Diagrams (ROBDDs).............................................5 1.4 Negative Edge.................................................6 1.5 Motivations......................................8 Chapter 2 Logic Synthesis Issues...............................................9 2.1 Gate-Diffusion Input (GDI)................................................9 2.1.1 Basic GDI Functions............................................10 2.1.2 A Design Methodology for Combinatorial Circuits.............................................12 2.2 Top-down PTL Design...............................................14 2.2.1 Pass-transistor Cell Library..............................................15 2.2.2 Circuit Inventor.............................................18 2.3 Mixed PTL/CMOS Design...............................................19 Chapter 3 Mixed CMOS/PTL Cell Library..............................................24 3.1 Pass-transistor Logic................................................25 3.2 Level Restoring Logic................................................28 3.3 Properties of Cells with different logic styles...............................................33 3.4 Synthesis Strategy.............................................40 Chapter 4 Decomposition Technique for BDD-based PTL Networks.............................................44 4.1 Classification of Boolean Function.............................................44 4.2 Synthesis Flow.................................................46 4.3 BDD Decomposition Technique............................................47 4.3.1 BDD Decomposition Rules................................................47 4.3.2 Considerations for BDD Decomposition........................................53 Chapter 5 Experimental Results and Conclusions..........................................55 5.1 Experimental Results..............................................55 5.2 Conclusions......................................58 REFERENCES...........................................59

    [1]S. B. Akers, “Binary Decision Diagrams”, IEEE Transactions on Computers, vol. c-27, no. 6, June 1978.

    [2]Z. Kohavi. Switching and Finite Automata Theory. Computer Science Press, New York, NY, 1978

    [3]R. K. Brayton, G. D. Hachtel, C. McMullen, and A. Sangiovanni-Vincentelli. Logic Minimization Algorithms for VLSI Synthesis. Kluwer Academic Publishers, Norwell, MA, 1984

    [4]R. Brayton, R. Rudell, A. Sangiovanni-Vincentelli, and A. Wang. “MIS: A Multiple-Level Logic Optimization System”. IEEE Transactions on Computer-Aided Design of Integrated Circuits, CAD-6(6):1062-1081, November 1987

    [5]R.E. Bryant, "Graph-Based Algorithms for Boolean Function Manipulation", IEEE Transactions on Computers, vol. c-35, no.8, Aug. 1986

    [6]J-C. Madre and J-P. Billon. “Proving Circuit Correctness Using Formal Comparison between Expected Behavior.” In Proceedings of the 25th Design Automation Conference, pages 205-210, June 1988

    [7]A. Morgenshtein, A. Fish, and I. A. Wagner. “Gate-Diffusion Input (GDI): A Power Efficient Method for Digital Combinatorial Circuits.” IEEE Transaction on Very Large Scale Integration (VLSI) System, Vol. 10, NO.5, October 2002.

    [8]K. Yano, Y. Sasaki, K. Rikino, and K. Seki. “Top-Down Pass-Transistor Logic Design” IEEE Journal of Solid-State Circuits. Vol. 31, NO.6, June 1996

    [9]S. Yamashita, K. Yano, Y. Sasaki, Y. Akita, H. Chikata, K. Rikino and K. Seki “Pass-Transistor/CMOS Collaborated Logic: The Best of Both Worlds” Symposium on VLSI Circuits Digest of Technical Papers page.31-32. 1997.

    [10]I. Sutherland, B. Sproull, and D. Harris, Logical Effort: Designing Fast CNOS circuits. San Mateo, CA: Morgan Kaufmann, p.7.

    [11]E. Shannon and W. Weaver, The mathematical Theory of Information. Urbana-Champaign: University of Illinois Press, 1969

    [12]K. Yano, T. Yamanaka, T. Nishida, M. Saito, K. Shimohigashi, and A. Shimizu. “A 3.8 ns CMOS 16 �e 16 multiplier using complementary pass-transistor logic.” IEEE Journal Solid State Circuits, Vol. 25, p.388, 1990.

    [13]H. Harvey-Horn, “User-defined benchmarks help evaluate IC physical libraries.” Electronics Design, p.80, Oct. 1993

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