成功大學博碩士論文系統

簡易檢索 / 詳目顯示

回結果列表

研究生：	汪羿齊 Wang, Yi-Chi
論文名稱：	獨立雙閘極鰭式電晶體快閃記憶體元件模型 Compact Model for Independent Double-gate FinFET Flash Memory
指導教授：	盧達生 Lu, Darsen
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 奈米積體電路工程碩士博士學位學程 MS Degree/Ph.D. Program on Nano-Integrated-Circuit Engineering
論文出版年：	2018
畢業學年度：	106
語文別：	英文
論文頁數：	59
中文關鍵詞：	氧化矽氮化物氧化物半導體、鰭式電晶體、快閃記憶體、雙閘極快閃記憶體
外文關鍵詞：	silicon-oxide-nitride-oxide semiconductor (SONOS), FinFET, flash memory, double-gate flash memory
相關次數：	點閱：143 下載：1
分享至:	分享至facebook 分享至twitter

查詢本校圖書館目錄查詢臺灣博碩士論文知識加值系統勘誤回報

本論文提出新型記憶體單元元件－獨立雙閘極鰭式電晶體快閃記憶體(Independent Double-Gate FinFET Flash Memory) 結構，使用Synopsys Hspice 基於BSIM-IMG進行建立描述元件物理模型，並且，透過Sentaurus TCAD 實驗軟體進行對應的元件建立，是採用前與後皆為SONOS(silicon–oxide–nitride–oxide–semiconductor)結構的對稱元件，擁有前控制閘極(Front Control Gate)與後控制閘極(Back Control Gate)，並且，前與後皆擁有獨立的電荷儲存層(Charge Storage Layer)，由於此結構特性，再進行記憶體陣列布局時，相較於傳統記憶體陣列，有較高的儲存密度，並且擁有獨立控制讀/寫的能力。
本研究將分別呈現基於BSIM-IMG Compact Model所描述建立的Single-Gate Flash Memory 與Independent Double-Gate Flash Memory Compact Model透過F-N Tunneling(Fowler-Nordheim Tunneling)穿隧機制進行寫入，研究清楚模擬出穿隧電流的指數變化，並且，顯示出前與後對稱結構的電位大小、電場大小以及臨界電壓的改變間接造成元件的ID電流變化，並且，探討臨界電壓的位移大小與寫入電壓與寫入時間的關係，完成元件物理模型。

This thesis proposes a memory unit cell structure called independent double-gate FinFET flash memory. Synopsys HSPICE is used to establish a physical model for describing a device based on the BSIM-IMG Compact Model. Sentaurus TCAD software is used to develop the corresponding device. The symmetrical device uses both front and back silicon-oxide-nitride-oxide semiconductor structures and has front and back control gates. The front and back have separate charge storage layers. The storage density of this memory array is higher than that of the conventional memory array. The proposed array has independent control of read/write capability.
This study presents single-gate flash memory and independent double-gate flash memory compact models based on the description of the BSIM-IMG Compact Model and program process through the Fowler-Nordheim tunneling mechanism. This study clearly simulates the exponential change of the tunneling current. Changes in the potential magnitude, electric field magnitude, and the threshold voltage of the front and back symmetric structures are shown to indirectly change the ID current of the device. The relationships between the magnitude of the displacement of the threshold voltage and the program voltage and program time are discussed to complete the physical model of the device.

Content
中文摘要		i
Abstract		ii
誌謝		iii
Content		iv
Figures Content	v
Chapter 1 Introduction	1
1-1.	Foreword	1
1-2.	Introduction to Memory	1
1-3.	Classification and Application of Flash Memory	2
1-4.	Research Motivation and Purpose	5
Chapter 2 Introduction and Operation Principle of Flash Memory	7
2-1 Basic Structure of Flash Memory Unit Cell	7
2-2 Changes in Threshold Voltage of Flash Memory	9
2-2-1. Change of Threshold Voltage for Floating Gate Structure	11
2-2-2. Change of Threshold Voltage for SONOS Structure	15
2-3 Flash Memory Program Physical Mechanism	20
2-3-1 Hot Electron Injection Mechanism	20
2-3-2. Fowler-Nordheim Tunneling Mechansim	22
2-4 Program Saturation of Flash Memory	26
2-4-1. Program Saturation of Floating Gate Structure Memory	26
2-4-2. Program Saturation of SONOS Structure Memory	28
Chapter 3 Simulation Results and Analysis	31
3-1 Experimental Simulation Introduction	31
3-2 Simulation and Experimental Software Environment Introduction	31
3-3 BSIM-IMG Compact Model Introduction	33
3-4 Single-Gate (UTB-SOI) FinFET Flash Memory Transistor Compact Model Simulation Results	35
3-4-1 Compact Model Device Description Structure and Parameters	35
3-4-2 Simulation Results	37
3-5 Independent Double-gate FinFET Flash Memory Transistor Model Simulation Results	44
3-5-1 Compact Model Device Structure and Parameters	44
3-5-2 Simulation Results	46
3-6 Oral Committee Question	55
Chapter 4 Conclusion	57
References		58




Figures Content
Figure 1-3.1 NAND flash memory array [1].	3
Figure 1-3.2 NOR flash memory array [1].	3
Figure 1-3.3. NAND and NOR flash applications [2].	4
Figure 1-4.1 Independent double-gate FinFET flash memory TCAD structure.	6
Figure 1-4.2 Independent double-gate FinFET flash memory transistor layout.	6
Figure 2-1.1 Flash memory unit cell structure.	7
Figure 2-1.2 Flash memory floating gate structure	8
Figure 2-1.3 Flash memory SONOS structure.	8
Figure 2-2.1 Flash memory unit cell during programming [3].	9
Figure 2-2.2 Flash memory unit cell during erasing [3].	10
Figure 2-2.3 Flash memory programming and erasing threshold voltage shift [4].	11
Figure 2-2-1.1 Flash memory floating gate structure capacitance diagram.	12
Figure 2-2-1.2 Flash memory floating gate structure equivalent capacitance circuit diagram.	12
Figure 2-2-2.1 Distribution of electric charge in flash memory with SONOS structure.	15
Figure 2-2-2.2 Trapping of charges in MOS capacitor [5].	16
Figure 2-2-2.3 Equivalent capacitance circuit for SONOS structure.	18
Figure 2-3-1.1 Hot carrier effect for MOSFETs [6].	21
Figure 2-3-1.2 Hot carrier injection for flash memory with floating gate structure [7].	22
Figure 2-3-2.1 F-N tunneling band diagram for flash memory program process [7].	23
Figure 2-3-2.2 F-N tunneling band diagram for flash memory erase process [7].	24
Figure 3-3.1 Independent double-gate FET structure [8].	34
Figure 3-3.2 UTBB SOI MOSFET structure [8].	34
Figure 3-4-1.1 Single-gate FinFET flash memory TCAD structure.	35
Figure 3-4-1.2 Single-Gate Equivalent Circuit	36
Figure 3-4-2.1 Single-gate flash memory compact model HSPICE simulation results.	41
Figure 3-4-2.2 Single-gate flash memory compact model. Vth versus program time from HSPICE simulation.	43
Figure 3-5-1.1 Independent double-gate FinFET flash memory TCAD structure	44
Figure 3-5-1.2 Independent double-gate Equivalent Circuit	46
Figure 3-5-2.1 Independent double-gate flash memory compact model HSPICE simulation results.	50
Figure 3-5-2.2 Independent double-gate FinFET flash memory compact model  Vth versus program time from HSPICE simulation.	53
Figure 3-5-2.3 Independent Double-Gate Coupling phenomenon	55
                                    

[1] ”成大資工 WiKi: NOR/NAND Flash介紹”, http://wiki.csie.ncku.edu.tw/embedded/Flash#flash%E5%8E%9F%E7%90%86%E4%BB%8B%E7%B4%B9 , (2018/06/19)
[2] Ruchiusha, ” flash memory technology”, https://www.slideshare.net/ruchiusha/07flash-memory-technology, (2018/06/19)
[3] MIKE RICHARDSON, “Floating Gates and Electron Tunnels: Flash Retains Data”, http://dataonfire.com/blog/2015/02/floating-gates-and-electron-tunnels-flash-retains-data/, ON FEBRUARY 2ND, 2015
[4] “UNDERSTANDING FLASH CHIP AT ITS CORE”, https://technoscooop.wordpress.com/2016/03/25/understanding-flash-chip-at-its-core/ , March 25, 2016
[5] Lenard Booth, “CHAPTER 6: MOSFET & RELATED DEVICES”, http://slideplayer.com/slide/10969353/# , (2018/06/19)
[6] Shiyanovskii, Yuriy, et al. "Hardware Trojan by hot carrier injection." arXiv preprint arXiv:0906.3832 (2009).
[7] Jinming, Liu, Mao Jian, and Li Yongmei. "Designing eraser of secret information in EEPROM." Computer Science and Education (ICCSE), 2010 5th International Conference on. IEEE, 2010.
[8] Khandelwal, Sourabh, et al. "BSIM-IMG: A compact model for ultrathin-body SOI MOSFETs with back-gate control." IEEE Transactions on Electron Devices 59.8 (2012): 2019-2026.
[9] K.K. Ng, G.W. Taylor, “Effects of hot-carrier trapping in n- and p-channel MOSFET's”, IEEE Transactions on Electron Devices, Volume: 30, Issue: 8, Aug 1983
[10] Groeseneken, Guido V. "Hot carrier degradation and ESD in submicrometer CMOS technologies: How do they interact?." IEEE transactions on device and materials reliability 1.1 (2001): 23-32.
[11] Song, Miryeong, Kenneth P. MacWilliams, and Jason CS Woo. "Comparison of NMOS and PMOS hot carrier effects from 300 to 77 K." IEEE Transactions on Electron Devices 44.2 (1997): 268-276.
[12] Guterman, Daniel C., et al. "An electrically alterable nonvolatile memory cell using a floating-gate structure." IEEE Transactions on Electron Devices 26.4 (1979): 576-586.

校內：2023-08-30公開
校外：不公開電子論文尚未授權公開，紙本請查館藏目錄

簡易檢索 / 詳目顯示

相關論文