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研究生: 劉炤德
Liu, Chao-Te
論文名稱: 抗靜電與電磁干擾防護之整合型陶瓷元件設計與製作
Design and Fabrication of Integrated Ceramic Device for Electrostatic Discharge and Electromagnetic Interference Protection
指導教授: 李文熙
Lee, Wen-Shi
學位類別: 碩士
Master
系所名稱: 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年: 2009
畢業學年度: 97
語文別: 中文
論文頁數: 76
中文關鍵詞: ZnO變阻器濾波器
外文關鍵詞: ZnO varsitor, filter
相關次數: 點閱:48下載:2
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  • 在本研究中,利用傳統之固態反應法,選用添加氧化鉍(Bi2O3)、氧化鈷(Co3O4)、三氧化二錳(Mn2O3)等氧化物於氧化鋅變阻器。本文選擇積層技術整合電容與電阻,將電阻內埋於陶瓷體加以低溫共燒。為了降低ZnO變阻器燒結溫度,添加數種燒結助劑於ZnO陶瓷,最後實做抗靜電與電磁干擾防護之整合型陶瓷元件,每一元件包含4個EMI濾波器與ESD保護的線路。為了實作電容-電阻-電容低通濾波器(capacitor-resistor-capacitor filter,C-R-C filter),濾波器的特性分析以π型2D電路進行,並進行3-dB 截止頻率為180 MHz低通濾波器設計,電氣特性以電磁軟體(Sonnet、HFSS)進行模擬,實際電路以積層陶瓷元件製程製作,更利用模擬結果與實作比較。
    Disc樣品實驗結果顯示,添加氧化釩(V2O5)、氧化硼(B2O3)可有效降低燒結溫度至至850℃,持溫時間亦可縮短至一小時內。元件量測結果顯示,實作元件電氣特性結果為3-dB截止頻率為204 MHz,900~2000 MHz至少衰減20 dB。

    In this study, ZnO varistors doped with Bi2O3, Co3O4, Mn2O3 were prepared using traditional solid-state reaction method. In this article, resistance paste prints in the green ceramic body for low-temperature co-fired process. In order to decrease the sintering temperature, adding several sintering aids to fabricate integrated ceramic device of electrostatic discharge and electromagnetic interference protection was investigated in this paper. There were 4 EMI filters and ESD protection lines in one device. The C-R-C low-pass filter circuit analysis was performed by one π-type equivalent circuit. The circuit with 3-dB cutoff frequency at 180 MHz was designed and evaluated by two electromagnetic simulators, Sonnet and HFSS. We used multilayer process to fabricate the device and compared the results of simulation with the performances of the device measurement.
    The result shows the sample was added V2O5、B2O3 to reduce the sintering temperature at 850℃ and holding time less than 1 hour. Finally, the measured results of the sample show 3-dB cutoff frequency at 204 MHz and minimum -20 dB attenuation from 900 MHz to 2000 MHz.

    第一章 緒論7 1-1背景與動機7 1-2研究目的8 1-3論文編排8 第二章 前人研究與基礎原理9 2-1變阻器 9 2-1.1壓敏陶瓷9 2-1.2氧化鋅變阻器11 2-2 ZnO-Bi2O3變阻器材料11 2-3變阻性質的生成機制15 2-3.1夾有晶界層之雙重蕭基能障15 2-3.2非歐姆特性16 2-4變阻電性之參數19 2-4.1晶界參數19 2-4.2非線性指數19 2-4.3漏電流20 2-4.5晶粒大小與電容、崩潰電場21 2-4.6箝制電壓21 2-4.7材料常數22 2-4.8介電損失22 2-5燒結理論22 2-5.1概述 22 2-5.2液相燒結23 2-6變阻器製程、結構與整合電路設計23 2-6.1積層元件製程23 2-6.2 積層元件結構 24 2-6.3 整合電路設計 28 第三章 實驗方法32 3-1實驗原料32 3-2 實驗設備33 3-3 實驗架構34 3-4 實驗流程35 3-4.1 粉末、漿料的製備36 3-4.2 胚體成形、燒結37 3-4.3 特性分析37 第四章 結果與討論39 4-1 積層元件實現方式39 4-1.1大電容實現方式39 4-1.2 積層製程多層化之優點40 4-2 降低陶瓷體燒結溫度的特性分析41 4-2.1陶瓷體燒結性質分析41 4-2.2電性分析50 4-3濾波電路模擬與元件實作、量測60 4-3.1低通濾波器模擬60 4-3.2元件實作65 4-3.3量測結果與分析68 第五章 結論與展望73 5-1 結論73 5-2 未來展望與探討 73 參考文獻74

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