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研究生：	劉育辰 Liu, Yu-Chen
論文名稱：	電流式數位類比轉換器之有限輸出阻抗校正 Calibration of Finite Output Impedance Effect for Current DACs
指導教授：	郭泰豪 Kuo, Tai-Haur
學位類別：	碩士 Master
系所名稱：	電機資訊學院 - 電機工程學系 Department of Electrical Engineering
論文出版年：	2008
畢業學年度：	96
語文別：	英文
論文頁數：	96
中文關鍵詞：	有限輸出阻抗、校正、數位類比轉換器
外文關鍵詞：	calibration, digital-to-analog converter, DAC, finite output impedance
相關次數：	點閱：79 下載：7
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在本論文中，我們分析了有限輸出阻抗在電流式數位類比轉換器中所造成的非理想效應，並提出了一個藉由輸入碼轉換的校正方法以改善有限輸出阻抗造成的非線性。藉由所提出的校正機制，使得數位類比轉換器在輸出阻抗不足其需求的情況下，仍保有良好的線性度。電流式數位類比轉換器對輸出阻抗的需求因而大大降低，因此傳統上用來增加輸出阻抗的疊接電晶體可被省略，使得轉換器即使操作在低電壓下，仍可具有相當大的輸出電壓擺幅。許多系統與電路設計上的考量，包含輸出阻抗模型，輸出阻抗需求，負載電阻不匹配等，也在本論文中被討論。
此外，我們也以0.18μm製程實現了一個12位元低阻抗，可在1.8V電壓下達到2.4V差動輸出擺幅的數位類比轉換器，來驗證此一技術。在低頻時，SFDR由校正前的56.36dB改善為83.77dB；在高頻時則由校正前的53.84dB改善為81.36dB。其核心面積為0.57mm2。

In this thesis, we analyze the finite output impedance effect through mathematical derivation and propose an effective calibration scheme named input code pre-distortion (ICPD) to improve the nonlinearity caused by finite output impedance. With this mechanism, insufficient output impedance is allowable in linear DAC design. Hence the output impedance requirement for current-steering DAC is relaxed. The cascode transistor used to boost output impedance in cascode configuration can be taken out. This makes the DAC has very wide output voltage swing under low supply voltage. Moreover, many design considerations on system and circuit level are discussed.
Besides, we implement a 12-bit DAC in 0.18μm CMOS process, which has ultra-wide output swing of 2.4-Vpp under 1.8V supply voltage, to verify the proposed calibration scheme. With this scheme, the SFDR is improved from 56.36dB to 83.77dB in low input frequency and from 53.84dB to 81.36dB at Nyquist rate. The active area is 0.57mm2.

Abstract (Chinese)     I 
Abstract (English)     II 
Acknowledgment         III 
Table of Contents      IV 
List of Tables         VI 
List of Figures        VII 
 
Chatper 1  Introduction                               1 
1  Motivation.....................................1 
2  Organization...................................2
   
Chapter 2 Fundamental of Digital-to-Analog Converter  4 
1  Introduction...................................4 
2  DAC Performances...............................5
2.1  Static Performances..........................5 
2.2  Dynamic Performances.........................9
3  Zero-Order Hold Response.......................13 
4  Nyquist-Rate Digital-to-Analog Converters......15 
4.1  Resistor-String Based DAC..................15 
4.2  Binary-Weighted Resistor DAC...............18 
4.3  Charge-Redistribution DAC..................21 
5  Current-Steering DAC...........................22
5.1  Fundamental of Current-Steering DAC........23
5.2  Current Source Mismatch....................27 
5.3  Output Impedance...........................30
5.4  Static Performance Improvements............32
5.5  Dynamic Performance Improvements...........37 
   
Chapter 3  Systematic Analysis and Design             42 
1  Finite Output Impedance Effect.................42 
1.1  The Impact of FOIE on Single-ended DAC.....42 
1.2  The Impact of FOIE on Differential DAC.....47 
2  Output Impedance Requirements of Current-Steering 
       DACs...........................................51 
3  Input Code Pre-Distortion Technique............55 
4  Modeling of Output Impedance with Output Voltage 
       Fluctuation....................................58 
5  Sensing of Output Impedance....................59 
6  Mismatch of Output Load Resistors..............61 
7  Consideration of Output Impedance Mismatch.....67 
   
Chapter 4  Circuit design and Physical Implementation 69 
1  DAC Architecture...............................69 
2  Current Cell Design in Wide Output Swing DAC...70 
3  Latch Circuit and D Flip-Flop..................71 
4  Return-to-Zero Circuit.........................73 
5  Clock Generator................................74 
6  Floorplan and Layout...........................75 
     
Chapter 5  Simulation and Measurement Results         79 
1  Simulation Results.............................79 
2  Measurement Setup..............................84 
2.1  Power Supply and Ground...................84 
2.2  Digital Input and Clock Termination.......85 
2.3  DAC Output Terminal.......................86 
2.4  Digital Input and Clock Termination.......87 
3  Comparison.....................................87 
 
Chapter 6  Conclusions                                90 
1  Conclusions...................................90 
2  Future Work...................................91 
   
References                                            93
                                    

[1] G. A. M. Van der Plas, J. Vandenbussche, W. Sansen, M. S. J. Steyaert and G. G. E. Gielen, “A 14-bit intrinsic accuracy Q2 random walk CMOS DAC,” IEEE J. Solid-State Circuits, vol. 34, no. 12, pp. 1708-1718, Dec. 1999.

[2] H. H. Chen, J. Lee, J. Weiner, Y. K. Chen and J. T. Chen, “A 14-b 150MS/s CMOS DAC with digital background calibration,” in Symp. VLSI Circuits Dig. Tech. Papers, June 2006, pp. 51-52.

[3] Yonghua Cong and Randall L. Geiger, “A 1.5-V 14-Bit 100-MS/s Self-Calibration DAC,” IEEE J. Solid-State Circuits, vol. 38, no. 12, pp. 2051-2060, Dec. 2003.

[4] Y. H. Lin, D. H. Lee, C. C. Yang and T. H. Kuo, “High-speed DACs with random multiple data-weighted averaging algorithm,” in Proc. IEEE ISCAS, May 2003, pp. I-993-I-996.

[5] Kok Lim Chan and Ian Galton, “A 14b 100MS/s DAC with Fully Segmented Dynamic Element Matching,” IEEE ISSCC Dig. Tech. Papers, Feb. 2006, pp. 2390-2399.

[6] Tao Chen and Georges G. E. Gielen, “The Analysis and Improvement of a Current-Steering DACs Dynamic SFDR—I: The Cell-Dependent Delay Differences,” IEEE Trans. Circuits Syst. I, vol. 53, no. 1, pp. 3-15, Jan. 2006.

[7] Tao Chen and Georges Gielen, “The Analysis and Improvement of a Current-Steering DACs Dynamic SFDR—II: The Output-Dependent Delay Differences,” IEEE Trans. Circuits Syst. II, vol. 54, no. 2, pp. 268-279, Feb. 2007.

[8] A A. Van den Bosch, M. A. F. Borremans, M. S. J. Steyaert and W. Sansen, “A 10-bit 1-GSample/s Nyquist current-steering CMOS D/A converter,” IEEE J. Solid-State Circuits, vol. 36, no. 3, pp. 315-324, March 2001.

[9] Chi-Hung Lin and Klaas Bult, “A 10-b, 500-MSample/s CMOS DAC in 0.6mm2”, IEEE J. Solid-State Circuits, vol. 33, no. 12, pp. 1948-1958, Dec 1998.

[10] M. J. M. Pelgrom, A. C. J. Duinmaijer and A. P. G. Welbers, “Matching properties of MOS transistors,” IEEE J. Solid-State Circuits, vol. 24, no. 5, pp. 1433-1439, Oct. 1989.

[11] A. Van den Bosch, M. Steyaert and W. Sansen, “An accurate statistical yield model for CMOS current-steering D/A converters,” in Proc. IEEE ISCAS, May 2000, pp. 105-108.

[12] A. van den Bosch, M. Steyaert and W. Sansen, “SFDR-Bandwidth Limitations for High Speed High Resolution Current Steering CMOS D/A Converters”, Proceeding of ICECS, vol. 3, pp. 1193-1196, Sept. 1999.

[13] Jose Bastos, Augusto M. Marques, Michel S. J. Steyaert and Willy Sansen, “A 12-bit Intrinsic Accuracy HighSpeed CMOS DAC,” IEEE J. Solid-State Circuits, vol. 33, no. 12, pp. 1959-1969, Dec. 1998.

[14] M. Tiilikainen, “A 14-bit 1.8-V 20-mW 1-mm2 CMOS DAC,” IEEE J. Solid-State Circuits, vol. 36, no. 7, pp. 1144-1147, July 2001.

[15] G. I. Radulov, P. J. Quinn, J. A. Hegt and A. H. M. van Roermund, “A start-up calibration method for generic current-steering D/A converters with optimal area solution,” in Proc. IEEE ISCAS, May 2005, pp.788-791.

[16] Martin Clara, Wolfgang Klatzer, Berthold Seger, Antonio Di Giandomenico andLuca Gori, “A 1.5V 200MS/s 13b 25mW DAC with Randomized Nested Background Calibration in 0.13μm CMOS,” IEEE ISSCC Dig. Tech. Papers, Feb. 2007, pp. 250-600.

[17] Qiuting Huang, Pier Andrea Francese, Chiara Martelli and Jannik Nielsen, “A 200MS/s 14b 97mW DAC in 0.18μm CMOS,” in IEEE ISSCC Dig. Tech. Papers, Feb. 2004, pp. 364-365.

[18] Alex R. Rugeja and Bang-Sup Song, “A Self-Trimming 14-b 100-MS/s CMOS DAC,” IEEE J. Solid-State Circuits, vol. 35, no. 12, pp. 1841-1852, Dec. 2000.

[19] Takahiro Miki, Yasuyuki Nakamura, Masao Nakaya, Sotoju Asai, Yoichi Akasaka and Yasutaka Horiba, “An 80-MhZ 8-bit CMOS D/A Converter,” IEEE J. Solid-State Circuits, vol. sc-21, no. 6, pp. 983-988, Dec. 1986.

[20] Kevin O’Sullivan, Chris Gorman, Michael Hennessy and Vincent Callaghan, “A 12-bit 320-MSample/s Current-Steering CMOS D/A Converter in 0.44mm2,” IEEE J. Solid-State Circuits, vol. 39, no. 7, pp. 1064-1072, July 2004.

[21] Alex R. Bugeja, Bang-Sup Song, Patrick L. Rakers and Steven F. Gilling, “A 14-b, 100-MS/s CMOS DAC Designed for Spectral Performance,” IEEE J. Solid-State Circuits, vol. 34, no. 12, pp. 1719-1732, Dec. 1999.

[22] S. Luschas and H. –S. Lee, “Output Impedance Requirements for DACs,” in Proc. IEEE ISCAS, May 2003, pp. I-861-I-864.

[23] Dongwon Seo and Gene H. McAllister, “A Low-Spurious Low-Power 12-bit 160-MS/s DAC in 90-nm CMOS for Baseband Wireless Transmitter,” IEEE J. Solid-State Circuits, vol. 42, no. 3, pp. 486-495, March 2007.

[24] Rudy van de Plassche, “CMOS Integrated Analog-to-Digital and Digital-to-Analog
Converters, 2nd Edition”, Kluwer Academic Publishers, CA, U.S.A. pp. 51-96, 2003.

[25] David A. Johns and Ken Martin, “Analog Integrated Circuit Design,” John Wiley &
Sons, Inc., New York, chapter 11-chapter 12, 1997.

[26] Behzad Razavi, “Design of Analog CMOS Integrated Circuits”, McGraw-Hill Publishers, Los Angeles, chapter 13, 2000.

[27] Hiroshi Takakura, Masashige Yokoyama and Akira Yamaguchi, “A 10 bit 80MHz Glitchless CMOS D/A Converter,” in Proc. IEEE CICC, May. 1991, pp. 26.5/1-26.5/4.

[28] Mark I. Montrose, “EMC and The Printed Circuit Board”, IEEE PRESS, New York, chapter 8, 1999.

[29] Evaluation Board AD9744 datasheet, Analog Devices, 2005.

校內：2011-08-20公開
校外：2011-08-20公開

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