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研究生： 陳彥甫
Chen, Yan-Fu
論文名稱： 將標準元件嵌入至具掃描架構的晶片中基於XOR的定量可測試功能塊之技術
Embedding Standard Cells into XOR-based C-testable Functional Blocks for Scan-Based Chips
指導教授： 李昆忠
Lee, Kuen-Jong
學位類別： 碩士
Master
系所名稱： 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年： 2023
畢業學年度： 111
語文別： 英文
論文頁數： 36
中文關鍵詞： 測試晶片設計 、可測試性設計 、XOR閘 、定量可測試性 、VH雙射函數
外文關鍵詞： Test chip design, design for testability, XOR-gate, C-testable, VH-bijection
相關次數： 點閱：36  下載：3 
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    • 在之前的研究中，已提出了一種由定量可測試功能塊所構成的二維陣列與掃描暫存器組成的具掃描架構的測試晶片架構。本論文中所提出的定量可測試功能塊包含了多個XOR模組並且具有VH雙射性質，即是此定量可測試功能塊具有雙射性質並且垂直或水平輸入的任何變化都會導致垂直和水平輸出同時發生改變。本論文也提出了一種創新的方法可將標準元件庫中的每個組合邏輯的標準元件系統性地嵌入到XOR模組中，如此一來，即使有多個錯誤存在於各標準元件中，也可以檢測到大部分標準元件的輸入向量錯誤 (包含固定型錯誤)。由於本論文所提出的定量可測試功能塊具有VH雙射性質和內部標準元件的完全錯誤覆蓋率，因此，應用此定量可測試功能塊的具掃描架構的測試晶片具有良好的可診斷能力。

    In the previous work, a scan-based test chip architecture composed of a two-dimensional array of C-testable blocks (CTBs) and scan registers is proposed. The CTBs proposed in this thesis contain several XOR modules and have the VH-bijection property, i.e., each CTB is bijective, and any change in either the vertical or horizontal input of a CTB will lead to changes in both vertical and horizontal outputs. This thesis also presents a novel method to systematically embed each combinational standard cell in a cell library to an XOR module such that almost all input pattern faults (including all stuck-at faults) in the standard cells can be detected even if multiple faults exist. Great diagnosability is achieved due to the VH-bijection property of CTBs, the full fault coverage property for faults in the standard cells inside CTBs, and the scan-based test chip architecture.

    摘要 i Abstract ii 致謝 iii TABLE OF CONTENTS iv TABLES v TABLE OF FIGURES vi CHAPTER 1 Introduction 1 CHAPTER 2 Background 4 2.1 VH-bijection 4 2.2 Input Pattern Fault (IPF) 5 2.3 Scan-based Test Chip Architecture 6 CHAPTER 3 C-testable Block & Test Chip Implementation 9 3.1 XOR-based CTB Design 9 3.2 Example of Linear Transform Matrix of VH-bijective Function 13 3.3 Test Chip Implementation Procedure 14 CHAPTER 4 Construction of XOR Modules 16 CHAPTER 5 Fault Analysis 19 5.1 Input Pattern Faults in Embedded standard cells 19 5.1.1 The auxiliary circuit and the XOR gate are fault-free 19 5.1.2 The auxiliary circuit or the XOR gate is also faulty 20 5.2 All Stuck-At Faults in XOR modules and CTBs 21 5.2.1 The fault located in the embedded cell 21 5.2.2 The fault located in the auxiliary circuit 22 5.2.3 The fault located at the primary input or the XOR gate 22 5.3 Fault existing in multiple XOR modules 23 5.4 All faults in CTBs 23 CHAPTER 6 Diagnosis Procedure 24 CHAPTER 7 Experiment Results 28 CHAPTER 8 Conclusions 33 References 34

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