本篇論文詳細討論一個精確的2.5伏特轉為1.8伏特的低壓降線性電壓穩壓器的設計與實現，這個電壓穩壓器包括錯誤放大器、高電流效率緩衝器、能隙參考電壓源和它的調整電路、熱關閉保護電路、電流限制保護電路，以及偏壓電路。傳統的線性電壓穩壓器的穩定度會隨著負載電流的增加而減少，這是由於線性電壓穩壓器天生的迴路特性以及隨時變動的操作環境所致，在這個設計中，二個技巧被使用來改善傳統線性低壓降電壓穩壓器穩定度的問題，包括米勒補償以及高電流效率緩衝器的使用。模擬結果顯示電壓穩壓器的穩定度幾乎不隨著負載電流的增加而減少，也幾乎不會因輸出電容的等效串聯電阻的變動而受其影響。為了降低穩壓器本身的雜訊，一個低雜訊的能隙參考電壓源的架構在這個設計中被採用。
整個電壓穩壓器全部晶片面積為1.2×1.2mm2，採用0.25μm，1P5M的CMOＳ混合信號製程。佈局後的模擬結果顯示電壓穩壓器當負載電流由0 mA變化到250 mA時，電壓穩壓器最大的輸出變化小於30 mV，整個電壓穩壓器可以輸出的電流大於250 mA，電源變動拒斥比超過60dB。

This thesis presents the design and implementation of precision 2.5V-to-1.8V low dropout linear regulators. The low dropout linear regulator includes the error amplifier, current-efficiency buffer, bandgap reference and its trimming network, thermal-shutdown protection circuit, current-limiting protection circuit and bias circuit. The stability of conventional linear regulators is decreasing with the load current increasing due to the innate characteristic of the feedback loop and changing working environments. Two techniques are utilized for solving this problem, including miller compensation and current-efficiency buffer. The simulation result shows the stability of this regulator isn’t almost reduced with load current increasing, and isn’t almost influenced by variation of equivalent series resistance of the output capacitor. Moreover, to reduce the intrinsic noise of the regulator itself, the bandgap reference with a low-noise topology is adopted.
The LDO voltage regulator is fabricated in 0.25μm 1P5M mixed-signal process, and occupies the total chip area of 1.2×1.2 mm2. The post-layout simulation results show maximum output variation is smaller than 30mV at a full current change from 0mA to 250 mA, maximum output current is larger than 250 mA, and PSRR (power supply rejection ratio) is larger than 60dB.

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