在掃瞄測試領域中，輸出壓縮的目的在於降低測試響應的資料量以及測試機台上測試頻道的需求量。然而，輸出壓縮所面臨的最大挑戰是如何處理失真的問題。壓縮器所造成的失真將影響錯誤涵蓋率，因而使得測試品質下降。由於目前掃瞄測試方法的趨勢是採用多掃瞄鏈架構並搭配輸入及輸出腳位的壓縮來達成同時降低測試時間和測試資料量的目的。所以，我們極需要一個適用於多掃瞄鏈架構的無失真輸出壓縮方法。再者，因為製程的進步，使得錯誤行為趨於複雜化。如何使輸出壓縮器傳出更多的錯誤資訊也是一個重要的議題。

　　在本篇論文中，我們針對多掃瞄鏈架構提出二個輸出壓縮方法。在第一個方法中，我們能在不影響定值錯誤之錯誤涵蓋率的情形下有效降低多掃瞄鏈的輸出腳位數量。第二個方法則提供了一個不需假設任何錯誤模型的壓縮方法。主要是提高壓縮器對錯誤位元的分辨能力，使錯誤傳遞出來的機率增加。

　　由實驗結果顯示，所提出的輸出壓縮方法在掃瞄鏈數目越多的情形下能達到越好的壓縮效果。因此，非常適合現今積體電路在掃瞄測試上的需求。

　The main purpose of output compaction in scan testing domain is to reduce output data volume and the number of output pins required to observe test responses. However, output compactors may induce aliasing, which happens when a faulty response maps to a fault-free signature. The information loss due to the compactors makes it hard to determine the exact fault coverage and thus leads to an uncertain test quality. At present, to reduce test time and test data volume concurrently, multiple scan chain design combined with scan input/output compaction techniques has become a trend. Consequently, a zero-aliasing compactor for multiple scan designs is urgently desired. Furthermore, as technology improves, the complex fault behaviors make it important for a compactor to propagate as much fault information as possible.

　In this thesis, two compaction techniques are proposed for the compression of scan chain outputs. In Method-I, full fault coverage for single stuck-at faults is maintained no matter how many scan chains are in a CUT. Moreover, the degree of error propagation is kept high in Method-II when no fault model is considered. We implement the proposed technique on some larger ISCAS’89 benchmark circuits. Experimental results show that high compaction ratio is achieved and the number of compactor outputs grows very slowly with the number of scan chains. Therefore, this method is well suitable for SoC testing.

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