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研究生： 林欣承
Lin, Hsin-Cheng
論文名稱： 應用於H.264幅內預測之方向偵測演算法
A Fast Direction Detection Algorithm for H.264 Intra Prediction
指導教授： 賴源泰
Lai, Yen-Tai
學位類別： 碩士
Master
系所名稱： 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年： 2010
畢業學年度： 98
語文別： 英文
論文頁數： 56
中文關鍵詞： H.264/AVC 、幅內預測 、方向偵測
外文關鍵詞： H.264/AVC, Intra Prediction, Direction Detection
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    • H.264/AVC動態影像壓縮編碼標準，近年來，它在視訊多媒體扮演著相當重要的角色，原因是它能在相同的影像品質下，擁有比以往的編碼標準更佳的壓縮效率。
    H.264/AVC能擁有這樣優異的壓縮效率不是沒有代價的，由於其編碼過程使用多幅參考畫面、可變區塊大小及1/4像素精確度的運動補償、畫面內相鄰區塊的幅內預測、以及使用內文適應性變動長度熵編碼或內文適應性二元算術熵編碼。上述方法能大幅降低編碼冗贅，但同時也增加大量的運算複雜度。
    進一步探究H.264/AVC的幅內預測，它可細分出9種4×4亮度區塊預測模式、4種16×16亮度區塊預測模式以及4種8×8彩度區塊預測模式，並使用碼率-失真最佳化計算出與原始畫面最相近的預測模式，因此需要相當繁複的運算才能得到兼具品質及效率的編碼結果。
    本論文將提出一種能快速偵測邊緣方向的演算法，預選出適當的幅內預測模式來降低編碼運算量，並透過參考軟體Joint Model驗證演算法，接著使用Verilog硬體描述語言實現其RTL之電路架構，係利用Synopsys®的Design Compiler與TSMC® 0.18μm製程作電路合成，最終得到可減少整體編碼70%運算量的幅內預測演算法以及運算速度高達202MHz的低複雜度硬體實現。

    H.264/AVC, the video compression standard, plays an important role of the multimedia in recent years, because H.264 can achieve better coding efficiency than previous video coding standards with the same video quality.
    To have such excellent compression efficiency, H.264 pays cost. The encode features can significantly reduce coding redundancy, but increase computational complexity by using motion compensation (including multiple reference frames, variable block size motion estimation and quarter-sample-accuracy motion vector), intra prediction and context-based adaptive entropy coding, such as CAVLC or CABAC.
    Within H.264 intra prediction, there are nine 4×4 luminance prediction modes, four 16×16 luminance prediction modes, and four 8×8 chrominance prediction modes. And the mode decision chooses the best mode by using rate-distortion optimization (RDO). If the encode obtains both good quality and high efficiency, it requires large amounts of RDO calculations.
    This thesis presents a mode selection approach to reduce computational time by using fast direction detection algorithm. We verify the proposed algorithm through the reference software Joint Model and implement the RTL code by Verilog hardware description language. We synthesize the digital circuit by using Design Compiler of Synopsys with the TSMC 0.18μm CMOS technology. Finally, the proposed intra prediction algorithm can reduce 70% computational time and the low complexity hardware can work up to 202MHz.

    Chapter 1 Introduction 1 1.1 H.264/AVC Video Compression Standard 1 1.2 Motivation 4 1.3 Thesis Organization 4 Chapter 2 Basic Concepts of H.264/AVC 5 2.1 Overview of H.264/AVC Standard 5 2.2 Basic Concepts of Intra Prediction 6 2.2.1 Intra 4×4 Luma Prediction Modes 7 2.2.1 Intra 16×16 Luma Prediction Modes 11 2.2.3 Intra 8×8 Chroma Prediction Modes 13 2.2.4 Rate-Distortion Optimization 16 2.3 Basic Concepts of Inter Prediction 17 2.3.1 Variable Block Size Motion Estimation 17 2.3.2 Quarter-Sample-Accurate Motion Vector 19 2.3.3 Multiple Reference Frame 21 2.3.4 Deblocking Filter 22 2.4 The Other Features 22 2.4.1 Integer Transform and Quantization 22 2.4.2 Entropy Coding 23 Chapter 3 Intra Prediction Algorithm 25 3.1 Conventional Intra Prediction Algorithm 25 3.2 Edge Detection Algorithm 26 3.3 Proposed Direction Detection Algorithm 28 3.3.1 Proposed Direction Detection Approach 28 3.3.2 Proposed Intra Prediction Algorithm 35 Chapter 4 Experimental Results and Implementation 36 4.1 Experimental Platform 36 4.2 Measuring Criteria 37 4.2.1 Peak Signal-to-Noise Ratio 37 4.2.2 Bit Rate 37 4.2.3 Speed Up 38 4.3 Experimental Results 48 4.4 Implementation 46 4.4.1 Hardware Architecture 46 4.4.2 Improvement on Data Flow Control 48 4.4.3 Synthesis Results 48 4.4.3.1 Timing Report 49 4.4.3.2 Area Report 51 4.4.4 Comparisons 52 Chapter 5 Conclusions 53 REFERENCES 54

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