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研究生： 徐菁偉
Hsu, Ching-wei
論文名稱： 應用於生醫感測器之1伏特13微瓦連續漸進式類比數位轉換器
A 1-V 13-μW on-Chip Successive Approximation Analog-to-Digital Converter for Bio-Sensing Applications
指導教授： 劉濱達
Liu, Bin-Da
學位類別： 碩士
Master
系所名稱： 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年： 2008
畢業學年度： 96
語文別： 英文
論文頁數： 69
中文關鍵詞： 連續漸進式類比數位轉換器 、低功率
外文關鍵詞： low-power, Successive Approximation Analog-to-Digital Conve
相關次數： 點閱：58  下載：4 
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    • 本論文為了實現一個應用於植入式生醫感測器的低電壓、低功率消耗的類比數位轉換器，提出了一個1伏特10位元低電壓低功率連續漸進式類比數位轉換器。利用全差動式的架構可以有效的減低雜訊及固定比較器的共模準位，使其對共模輸入準位的要求較低。為了減低功率消耗，採用了自我時間式位元轉換使前置放大器有接近兩倍的時間可以穩定，且當轉換完成時將所有元件的電流關閉。此外，前置放大器的元件操作在弱反轉區，皆可以有效的減低功率消耗。
    本論文使用0.18 微米一層多晶矽六層金屬之互補式金氧半製程，實現一個供應電壓為1伏特，輸出為10位元的數位訊號，取樣頻率為200千赫低功率消耗類比數位轉換器。在輸入訊號為20.04千赫時，連續漸進式類比數位轉換器的訊號對於雜訊及諧波失真比為 61.73 dB，而微分非線性誤差在 ±0.3 LSB 的範圍，積分非線性誤差在 ±0.2 LSB 的範圍，不含偏壓電路，整個電路的功率消耗為 13微瓦。

    This thesis describes a low supply voltage and low-power integrated analog-to-digital converter (ADC) for implantable bio-medical sensor applications. A 1-V 10-bit successive approximation ADC is proposed. The fully differential architecture can suppress the noise effectively and allow a rail-to-rail input voltage range. The settling time of the preamplifier of the comparator becomes nearly two times by using a self-timed bit-cycling technique. In addition, the component will shut down when the conversion is finished. Therefore, the power consumption can be reduced.
    This successive approximation ADC with a 1-V supply voltage has been design in 0.18-μm CMOS process without low threshold MOS devices. The SNDR is 61.73 dB with the input frequency of 20.04 kHz and sample frequency of 200 kHz. The INL and DNL are between ±0.3LSB, and total power consumption without biasing circuit is 13-μW. FOM of the pre-layout simulation achieves 0.067 (pJ/conv.) without accounting biasing circuit.

    Contents List of Tables iv List of Figures v Chapter 1 Introduction 1 1.1 Motivation 1 1.2 Thesis Organization 3 Chapter 2 Fundamentals of ADC 5 2.1 Principles of ADC 5 2.2 Basic Concepts 6 2.2.1 Introduction to ADCs 6 2.2.2 Ideal ADC 8 2.2.3 Quantization Noise 9 2.3 Specifications 12 2.3.1 Static Specifications 12 2.3.2 Dynamic Specifications 15 2.4 Classification 16 2.5 ADC Architectures 17 2.5.1 Flash ADC 17 2.5.2 Two-Step ADC 19 2.5.3 Pipelined ADC 20 2.5.4 Successive Approximation ADC 21 Chapter 3 Circuit Blocks of Successive Approximation ADC 25 3.1 Digital-to-Analog Converters 27 3.2 Digital-to-Analog Converter Using a Split Array 28 3.3 Comparator 29 3.3.1 Comparator Offset Cancellation 30 3.3.2 Input Offset Storage 30 3.3.3 Output Offset Storage 32 3.3.4 Multistage Offset Storage 33 Chapter 4 Building Block Design 35 4.1 Timing of Proposed Successive Approximation ADC 36 4.1.1 Timing Diagram 36 4.1.2 Self-Timed Bit-Cycling 37 4.2 The Architecture of Proposed Successive Approximation ADC 39 4.3 Digital-to-Analog Converter 40 4.3.1 Digital-to-Analog Converter 40 4.3.2 Split Capacitor Array of Digital-to-Analog Converter 44 4.4 Bootstrapped Switch 50 4.5 Comparator 52 4.5.1 Preamplifier 53 4.5.2 Latch 54 4.5.3 Simulation results 55 Chapter 5 Experimental Results 57 5.1 Static Specifications 57 5.2 Dynamic Specifications 59 5.3 Layout Consideration 62 5.3 Performance Comparison of ADCs 64 Chapter 6 Conclusions and Future Work 65 6.1 Conclusions 65 6.2 Future Work 66 References 67

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