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研究生: 何俊緯
Ho, Chun-Wei
論文名稱: 具快速追隨電壓準位能力之動態電壓調節器
Dynamic Voltage Scaling (DVS) Regulator with Fast Reference Tracking Ability
指導教授: 張簡樂仁
Chang-Chien, Le-Ren
學位類別: 碩士
Master
系所名稱: 電機資訊學院 - 電機工程學系
Department of Electrical Engineering
論文出版年: 2017
畢業學年度: 105
語文別: 英文
論文頁數: 68
中文關鍵詞: 快速動態電壓調整適應性導通時間控制法直流-直流降壓穩壓器
外文關鍵詞: Fast dynamic voltage scaling (FDVS), Adaptive on-time (AOT) control, DC-DC buck converter
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  • 本論文提出一個具有快速電壓追隨能力的動態電壓降壓調節器,以達到快速動態電壓調整功能。經由一組輔助電容搭配快速電荷分配控制法,能夠讓此電壓調節器的輸出電壓在不同電壓準位間快速切換,並減少電路設計的複雜度。此外,搭配適應性導通時間控制法,能使這個電壓調節器具備快速負載暫態響應能力,並在不同輸出電壓準位間仍能保持固定的切換頻率。
    本晶片使用TSMC 0.35µm 2P4M 5V混合訊號製程,晶片尺寸為1.674*1.849 mm2。此電壓調節器輸入電壓範圍為4.2V~5V,輸出電壓準位分別為1.8V及3.3V,負載電流範圍為10mA~400mA。實驗顯示對於1.5V步階動態電壓調節,輸出電壓在1µs內穩定。

    A dynamic voltage scaling (DVS) buck regulator with fast reference tracking ability is proposed. With a fast charge distribution control loop using two auxiliary capacitors, the output voltage of this buck regulator is able to be quickly switched between different output voltage levels without complex auxiliary circuit and control. Besides, the adaptive on-time (AOT) control is applied to this regulator for enhancing fast load transient response and maintaining constant switching frequency.
    This chip is fabricated by TSMC 0.35 µm 2P4M 5V mixed-signal process. The chip area is 1.674*1.849 mm2 including pads. The input voltage range is from 4.2V to 5V to provide two output voltage levels, 1.8V and 3.3V. The load current ranges from 10mA to 400mA. From a 1.5V step DVS transient test, the output voltage is settled within 1 µs.

    摘要 I Abstract II Acknowledgements III Contents IV List of Tables VII List of Figures VIII Chapter 1 Introduction 1 1.1 Background 1 1.2 Motivation 3 1.3 Thesis Organization 4 Chapter 2 Fundamentals of DC-DC Buck Converters 5 2.1 Definition of DC-DC Buck Converters 5 2.1.1 Line Regulation and Load Regulation 5 2.1.2 Load Transient Response 5 2.1.3 DVS Transient Response 6 2.1.4 Efficiency 7 2.2 Introduction to Conventional DC-DC Buck Converters 9 2.2.1 Structure 9 2.2.2 Operation Principle 10 2.2.3 Voltage Mode Control [10] 12 2.2.4 Current Mode Control [10] 14 2.2.5 Comparison 16 Chapter 3 Ripple-Based Control of Switching Converter 17 3.1 Introduction of Ripple-Based Control Method [11] 17 3.2 Hysteretic Control [10] 19 3.3 Constant On-Time Control [11][12] 20 3.4 Constant Off-Time Control [11] 23 3.5 V2 Control [13][14] 24 3.6 Comparison 26 Chapter 4 Switchable Output Capacitor for FDVS 27 4.1 DVS Transient Response Enhancement 27 4.2 Operation of the Proposed Control Scheme 28 4.3 Charge Distribution of the Proposed Control Scheme 29 4.3.1 Voltage Over/under-shoot Issue 30 4.3.2 Settling Time Issue 35 Chapter 5 Circuit Implementation 38 5.1 System Structure 38 5.2 Circuit Design 39 5.2.1 Bias Circuit 39 5.2.2 Comparator [19] 40 5.2.3 Operational Amplifier 41 5.2.4 Bandgap Voltage Reference [20] 42 5.2.5 Adaptive On-Time Generator [21][22] 44 5.2.6 Soft-Start Circuit 46 5.2.7 Zero Current Detection 46 5.2.8 DVS Controller 47 5.2.9 Dead-Time Controller 48 5.2.10 Power MOSFET [23] 49 5.3 IC Layout 51 Chapter 6 Simulation and Experimental Results 53 6.1 Simulation Results 53 6.1.1 Simulation Condition 53 6.1.2 Steady State 53 6.1.3 Transient Response 55 6.2 Experimental Results 58 6.2.1 Measurement Condition 58 6.2.2 Steady State Waveforms 58 6.2.3 Transient Response Waveforms 60 Chapter 7 Conclusions and Future Works 64 7.1 Conclusions 64 7.2 Future Works 64 Bibliography 66

    [1] I. Pressman, Switching Power Supply Design, McGraw-Hill, 1999.
    [2] M. Hiraki, T. Ito, A. Fujiwara, T. Ohashi, T. Hamano, T. Noda, “A 63-μW Standby Power Microcontroller with On-Chip Hybrid Regulator Scheme,’’ IEEE J. Solid-State Circuits, vol. 37, no. 5, pp. 605-611, May 2002.
    [3] Shen-Yu, P., H. Tzu-Chi, L. Yu-Huei, C. Chao-Chang, C. Ke-Horng, L. Ying-Hsi, L. Chao-Cheng, T. Tsung-Yen, H. Chen-Chih, C. Long-Der, and Y. Cheng-Chen, “Instruction-Cycle-Based Dynamic Voltage Scaling Power Management for Low-Power Digital Signal Processor With 53% Power Savings,’’ IEEE J. Solid-State Circuits, vol. 48, pp. 2649-2661, 2013.
    [4] Lee, Y. H., S.Y. Peng, C.C. Chiu, A. C. H. Wu, K. H. Chen, Y. H. Lin, S. W. Wang, T. Y. Tsai, C. C. Huang, and C. C. Lee, “A Low Quiescent Current Asynchronous Digital-LDO With PLL-Modulated Fast-DVS Power Management in 40 nm SoC for MIPS Performance Improvement,’’ IEEE J. Solid-State Circuits, vol. 48, pp. 1018-1030, 2013.
    [5] Y. H. Lee, C. C. Chiu, S. Y. Peng, K. H. Chen, Y. H. Lin, C. C. Lee, C. C. Huang, and T. Y. Tsai, “A Near-Optimum Dynamic Voltage Scaling (DVS) in 65-nm Energy-Efficient Power Management with Frequency-Based Control (FBC) for SoC System,” IEEE J. Solid-State Circuits, vol. 47, no. 11, pp. 2563–2575, Nov. 2012.
    [6] C. Zheng, D. S. Ma. “Design of Monolithic CMOS LDO Regulator with Coupling and Adaptive Transmission Control for Adaptive Wireless Powered Bio-Implants,” IEEE Trans Circuits Syst. I, Reg. Papers, Vol. 58, pp. 2377-2386, Oct. 2011.
    [7] G. Wang et al. “Design and Analysis of an Adaptive Transcutaneous Power Telemetry for Biomedical Implants,” IEEE Trans. Circuits Syst. I, Reg. Papers, Vol. 52, pp. 2109-117, Oct. 2005.
    [8] C. F. Lee, P. K. T. Mok, “A Monolithic Current-Mode CMOS DC-DC Converter with On-Chip Current Sensing Technique,” IEEE J. Solid-State Circuits, vol. 39, no. 1, pp. 3-14, Jan. 2004.
    [9] W. R. Liou, M. L. Yeh, and Y. T. Kuo, “A High Efficiency Dual-Mode Buck Converter IC for Portable Applications,” IEEE Trans. Power Electron, vol. 23, no. 2, pp. 667–677, Mar. 2008.
    [10] Marty Brown, “Power Supply Cookbook,” Butterworth- Heinemann, 1994.
    [11] Richard Redl, and Jian Sun, “Ripple-Based Control of Switching Regulators — An Overview,’’ IEEE Trans. Power Electron, vol. 24, no. 12, pp. 2669–2680, Dec. 2009.
    [12] Y. C. Lin, C. J. Chen, Dan Chen, and Brian Wang, “A Ripple-Based Constant On-Time Control With Virtual Inductor Current and Offset Cancellation for DC Power Converters,’’ IEEE Trans. Power Electron, vol. 27, no. 10, pp. 4301–4310, Oct. 2012.
    [13] S. Qu, “Modeling and Design Considerations of V2 Controlled Buck Regulator,’’ in Proc. IEEE APEC’01, Anaheim, California, pp. 507–513, 2001.
    [14] F. Wang, J. Xu, J. Xu, “Small-Signal Model of V2 Control Technique with Compensation”, Proc. IEEE ICCCAS Conf., pp. 1358-1362, 2004.
    [15] Patrick Y. Wu and Philip K. T. Mok, “A Monolithic Buck Converter With Near-Optimum Reference Tracking Response Using Adaptive-Output-Feedback,” IEEE J. Solid-State Circuits, vol. 42, no. 11, pp. 2441-2450, Nov. 2007.
    [16] S. H. Chien, T. H. Hung, S. Y. Huang, and T. H. Kuo, “A Monolithic Capacitor-Current-Controlled Hysteretic Buck Converter With Transient-Optimized Feedback Circuit,” IEEE J. Solid-State Circuits, vol. 50, no. 11, pp. 2524-2532, Nov. 2015.
    [17] F. Su, W. H. Ki, and C. Y. Tsui, “Ultra Fast Fixed-Frequency Hysteretic Buck Converter With Maximum Charging Current Control and Adaptive Delay Compensation for DVS Applications,” IEEE J. Solid-State Circuits, vol. 43, no. 4, pp. 815-822, Apr. 2008.
    [18] L. Cheng, Y. Liu, and W. H. Ki, “A 10/30 MHz Fast Reference-Tracking Buck Converter With DDA-Based Type-III Compensator,” IEEE J. Solid-State Circuits, vol. 49, no. 12, pp. 2788-2799, Dec. 2014.
    [19] D. A. John, K. Martin, “Analog Integrated Circuit Design”, Wiley, 1999.
    [20] K. N. Leung, and Philip K. T. Mok, “A Sub-1-V 15-ppm/°C CMOS Bandgap Voltage Reference Without Requiring Low Threshold Voltage Device,” IEEE J. Solid-State Circuits, vol. 37, no. 4, pp. 526-530, Apr. 2002.
    [21] Biranchinath Sahu, and Gabriel A. Rincón-Mora, “An Accurate, Low-Voltage, CMOS Switching Power Supply With Adaptive On-Time Pulse-Frequency Modulation (PFM) Control,” IEEE Trans .Circuits and Systems, vol. 54, no. 2, pp. 312-321, Feb. 2007.
    [22] C. H. Tsai, S. M. Lin, and C. S. Huang, “A Fast-Transient Quasi-V2 Switching Buck Regulator Using AOT Control With a Load Current Correction (LCC) Technique,” IEEE Trans. Power Electron, vol. 28, no. 8, pp. 3949–3957, Aug. 2013.
    [23] A. Hastings, “The Art of Analog Layout”, Englewood Cliffs, NJ: Prentice-Hall, 2001.

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