在過去的二十年裡，測試資料量壓縮在實務上已成為超大積體電路設計中用於降低整體測試成本的重要技術。在可測試性設計(Design for Testability)的規劃期間，了解使用不同數量的輸入/輸出通道對測試涵蓋率、測試週期和測試資料量的影響非常重要。在這篇論文中，針對不同輸入通道數，我們提出了一種能有效率預測測試資料量的方法，此方法主要應用於嵌入式確定性測試（EDT）測試壓縮技術。並且我們可以將預測之結果用於快速決定擁有最少或接近最少測試資料量的掃描組態配置。和目前使用的反複試驗方法相比，使用這種方法可以使整體DFT規劃時之ATPG運行時間減少10倍以上。

Over the past two decades, test data compression has become a de facto technology used in large industrial designs to reduce the overall test cost. During DFT planning, it is very important to understand the impact of using different numbers of input/output channels on test coverage, test cycles, and test data volume. In this thesis, an efficient method to predict the test data volume with different input channel counts using the Embedded Deterministic Test (EDT) compression technology is proposed. The results can then be used to quickly determine the scan configuration that results in the least or near least test data volume. With this method, the total ATPG run time can be reduced by a factor of more than 10X compared to the currently used trial-and-error method.

[1] L.T. Wang, C.W. Wu, and X. Wen, VLSI Test Principles and Architectures: Design for Testability, Morgan Kaufmann, 2006.
[2] N.A. Touba, “Survey of test vector compression techniques,” IEEE Design & Test of Computers, vol. 23, pp. 294-303, July-Aug. 2006.
[3] R. Kapur, S. Mitra, and T.W. Williams, “Historical perspective on scan compression,” IEEE Design & Test, vol. 25, no. 2, pp. 114-120, 2008.
[4] K-J. Lee, J-J. Chen, and C-H. Huang, “Using a single input to support multiple scan chains,” Proc. ICCAD, 1998, pp. 74-78.
[5] L.-T. Wang, X. Wen, S. Wu, Z. Wang, Z. Jiang, B. Sheu, and X. Gu, “VirtualScan: test compression technology using combinational logic and one-pass ATPG,” IEEE Design & Test, vol. 25, no. 2, pp. 122-130, 2008.
[6] A. Chandra, R. Kapur and Y. Kanzawa, “Scalable Adaptive Scan (SAS),” Proc. DATE, 2009.
[7] B. Koenemann, “LFSR-coded test patterns for scan designs,” Proc. ETC, 1991, pp. 237-242.
[8] J. Rajski, J. Tyszer, M. Kassab, N. Mukherjee, N. Tamarapalli, and J. Qian, “Embedded deterministic test for low cost manufacturing,” IEEE Design & Test, vol. 20, pp. 58-66, 2003.
[9] J. Rajski et al., “Method and Apparatus for Selectively Compacting Test Responses,” US Patent 7,805,649.
[10] “Tessent® Shell Reference Manual”, Mentor, Siemens, 2018.
[11] C.-H. Wu et al., “Deep Learning Based Test Compression Analyzer,” Proc. ATS, 2019.
[12] M. Kassab et al., “Dynamic Channel Allocation for Higher EDT Compression in SoC Designs,” Proc. ITC, 2010.
[13] J. Janicki et al., “EDT Channel Bandwidth Management in SoC Designs with Pattern-Independent Test Access Mechanism,” Proc. ITC, 2011.
[14] F.J. Tsai et al., “Efficient Prognostication of Pattern Count with Different Input Compression Ratios” IEEE European Test Symposium (ETS), 2020.