因應目前對於每秒億次取樣以上低解析度類比數位轉換器的需求，在這一篇論文中，我們提出了一個每秒二億次取樣的單一類比路徑六位元快閃式類比數位轉換器。這個轉換器針對一些高速的應用，像是硬碟讀寫頭及高速有線傳輸，進行最佳化的設計。

　　這裡所提出的類比數位轉換器，包含了一個擬差動式開迴路的取樣電路、一個比較器陣列、一個四通道六十四對六的編碼器以及一個產生各種所需時脈訊號的系統。在這一個轉換器中，我們所使用的比較器，並不是傳統上所使用的閂鎖式比較器，而是採用了連續時間式的比較器。這是為了簡化設計上的困難度，並且移除了閂鎖器與重設開關這些強大的雜訊來源。為了消除電晶體本身的隨機漂移所造成的影響，在前置放大器與第一級比較器的陣列中，我們使用電阻性平均網路這個技巧來改善電路的效能。

　　這個電路設計透過國家晶片系統設計中心由台積電進行下線驗證。這個電路使用的製程是0.18 um CMOS 1P6M製程，這個晶片所佔面積約為3.57 mm2。整個電路在操作時的消耗功率為 360 mW ，並且整個電路使用的供應電壓為 1.8 V。 這個電路的佈局後模擬顯示，在系統時脈為2 GHz，輸入訊號頻率為200 MHz的情況下，所得到的訊號對雜訊與失真比為 32.52 dB。而在初步的量測驗證後發現，在系統時脈為500 MHz且輸入訊號頻率分為50 MHz與100 MHz的時候，量測到的訊號對雜訊與失真比分別為28.58 dB與23.46 dB。

　　除了所提出的類比數位轉換器的設計與實現之外，我們也對電阻性平均網路與輸入訊號頻率之間的關係加以探討。分析的結果顯示輸入訊號的頻率會形成在選擇負載阻抗值對平均電阻阻抗值比例上的一個上限。根據這個分析，我們得以對所提出的高速快閃式類比數位轉換器的效能做出最佳化。

　Owing to the growing demand for GS/s level ADCs nowadays, a 6-bit single analog path 2 GS/s flash ADC is proposed in this thesis. This ADC is optimized to operate in high speed applications such as hard disk read channel and high speed communication system.

　The proposed ADC architecture consists of a pseudo-differential open-loop track-and-hold circuit, a comparator array composed of 64 comparators and 16 dummy comparators, a four-channel 64-to-6 ROM-based encoder, and a clock generation and distribution system. Instead of traditional latch-based comparators, continuous-time comparators are employed to simplify block design and remove noises induced by switches and latches. Moreover, the preamplifiers and 1st stage comparators are averaged by using the resistive network technique.

　This work is fabricated in TSMC 0.18-m mixed signal 1P6M salicide 1.8V/3.3V CMOS technology. The chip occupies 3.57 mm2 die area and the digital part occupies half of the area. The post-layout simulated signal to noise and distortion ratio with 200 MHz input is 32.52 dB at 2 GS/s. The total power consumption is about 360 mW from a 1.8 V supply. The measured signal to noise and distortion ratios at 500 MS/s with 50 and 100 MHz input are 28.58 dB and 23.46 dB, respectively.

　In addition to the design and implementation of a high speed flash ADC, the relation between the resistive averaging network and input signal frequency is analyzed. The analysis shows that the input frequency sets an upper bound for the ratio of the load resistance to the averaging resistance. With this bound, the high frequency performance of the proposed flash ADC is optimized.

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