隨著積體電路在設計與製程的快速發展，整合至系統單晶片的電路設計越來越多，系統效能的瓶頸逐漸由電路模組的內部設計，延伸到各個電路模組之間的溝通。為了避免匯流排成為系統單晶片發展上的瓶頸，設計一個能有效地完成模組之間資料傳輸之高效能匯流排，逐漸成為一個系統單晶片是否能有效率地運作的關鍵。
系統中多個核心電路通常來自於不同的供應者，亦各自擁有不一樣的溝通介面，導致系統整合往往相當耗時費力。因此系統匯流排在設計上除了要保有電路設計的彈性與可重複使用性之外，也要具備容易與其他電路整合的特性。在這種需求的考量下，採用國際標準之溝通介面以縮短整合時程自然成為一種趨勢。開放核心協定國際合作組織(OCP-IP)在傳輸上定義了一個高效能、獨立於匯流排且公開的標準介面，其目的為藉由彈性的標準介面設計方式達到電路之間「隨插即用」(Plug and Play)的理想，以降低電路溝通的難度與系統整合耗費的時間，也增加電路設計重複使用的效益。
在本篇論文裡，我們致力於：1) 發展支援多種高效能傳輸模式之匯流排設計、 2) 提供快速模擬且具有設計彈性之匯流排模組、3)實現硬體電路以協助使用者進行完整之設計與驗證流程。主要的成果為提出一個基於部分或完全交叉開關的架構，且符合開放核心協定之標準介面之高效能匯流排設計，可支援多個主從電路設計的仲裁管理機制、多筆平行運算、爆發(Burst)模式、不須依序(Out-of-order)傳輸等，同時具有允許資料傳輸重新排程的能力，有效地減少資料傳輸時間與提升匯流排之頻寬，彌補傳統匯流排架構之不足，並解決系統整合面臨的挑戰。本設計亦同時加入參數化的考量，保留匯流排的彈性，系統整合者可以設定參數得到多種匯流排的組合，協助使用者選擇開發理想的系統架構，滿足各種應用與系統所需要的效能。實驗結果分析顯示，相較於傳統的匯流排，本論文所提出的匯流排設計能大幅降低資料傳輸的時間並進而有效地提升整體效能。

Due to the rapid progress in IC design and development, the number of integrated IP cores in SOC designs is increasing, and the communication between IP cores are increasing accordingly. However, the traditional bus design is out-of-date to deal with the large amount of communication data, and the communication architecture becomes one of the bottlenecks of system performance of System-on-Chip (SOC) designs. As a result, it is a critical design issue about how to develop advanced bus architecture to satisfy the high performance requirements and improve the overall performance of SOC designs.
Moreover, many of the cores in SOC designs come from different designers or vendors who have different communication interfaces. Therefore, the bus design should not only be flexible and reusable but also easy to be integrated with other IP designs. The bus interface plays an important role in determining the efforts of system integration, so it is efficient to ease the complex integration flow by adopting standard protocols of interface for bus models for bus models. Open Core Protocol (OCP) is an freely available and on-chip interconnect independent interface standard, which provides flexible, scalable and configurable interfaces design to match the communication requirements associated with different IP cores and achieve the goal of “Plug and Play.” OCP further reduce the effort of system integration and increase the reusability of IP as well.
In this thesis, we focus on: 1) develop the high performance bus design which supports several advanced transfer functionalities, 2) providing the flexible transaction level bus models having OCP standard interface with high simulation speed, and 3) implementation of RTL models for complete design and verification procedure. We proposed the full-crossbar or partial-crossbar high performance bus architecture with OCP standard interfaces.
The proposed bus model adopts the OCP standard for bus interfaces to shorten integration time. It supports the multi-master to multi-slave arbitration scheme and several advanced communication features including parallel, pipeline, burst, multiple outstanding and out-of-order transactions. Especially, the out-of-order transaction allows the SOC system re-scheduling the responses, such that the latency of transactions is decreasing and the bus throughput and system performance are improved. Besides, the parameterized bus design is flexible. System developers are able to adjust the parameters to select the suitable system configuration to meet the performance requirements of various applications of systems. The simulation results show that the proposed bus design reduces the long transaction latency efficiently and further improves overall system performance.

[1] Open Core Protocol International Partnership (OCP-IP), www.ocpip.org.
[2] L. Cai and D. Gajski, “Transaction level modeling: an overview,” in Proc. First IEEE/ACM/IFIP International Conference on Hardware/Software Codesign and System Synthesis, pp. 19-24, 2003.
[3] Advanced Microcontroller Bus Architecture (AMBA) Specification Rev 3.0, http://www.arm.com.
[4] David C.-W. Chang, I.-T. Liao, J.-K. Lee, W.-F. Chen, S.-Y. Tseng, and C.-W. Jen, “PAC DSP core and application processors,” in Proc. IEEE International Conference on Multimedia and Expo, pp. 289-292, 2006.
[5] Open SystemC Initiative (OSCI), SystemC v.2.0 Specification. http://www.systemc.org.
[6] T. Grötker, G. Martin, and S. Liao, System design with SystemC, Kluwer Academic Publishers, 2002.
[7] D. C. Black and J. Donovan, SystemC: From the ground up, Kluwer Academic Publishers, 2004.
[8] ARM Ltd. Web Site, http://www.arm.com.
[9] K. Lahiri, A. Raghunathan, and G. Lakshminarayana, “The LOTTERYBUS on-chip communication architecture,” in IEEE Trans. on Very Large Scale Integration (VLSI) Systems, vol. 14, pp. 596-608, 2006.
[10] J. Yoo, D. Lee, S. Yoo, and K. Choi, “Communication architecture synthesis of cascaded bus matrix,” in Proc. Asia and South Pacific Design Automation Conference, pp.171-177, 2007.
[11] S. Malik and X. Zhu, “A hierarchical modeling framework for on-chip communication architectures,” in Proc. IEEE/ACM International Conference on Computer-Aided Design, pp. 663-670, 2002.
[12] O. Ogawa, S. Bayon de Noyer, P. Chauvet, K. Shinohara, Y. Watanabe, H. Niizuma, T. Sasaki, and Y. Takai, “A practical approach for bus architecture optimization at transaction level,” in Proc. Design, Automation and Test in Europe Conference and Exhibition, pp. 176-181, 2003.
[13] M. Caldari, M. Conti, M. Coppola, S. Curaba, L. Pieralisi, and C. Turchetti, “Transaction-level models for AMBA bus architecture using SystemC 2.0,” in Proc. Design, Automation and Test in Europe Conference and Exhibition, pp. 26-31, 2003.
[14] S. Pasricha, D. Nikil, and M. Ben-Romdhane, “Extending the transaction level modeling approach for fast communication architecture exploration,” in Proc. Design Automation Conference, pp. 113-118, 2004.
[15] S. Dongwan, A. Gerstlauer, P. Junyu, R. Domer, and D.D. Gajski, “Automatic generation of transaction level models for rapid design space exploration,” in Proc. International Conference on Hardware/Software Codesign and System Synthesis, pp. 64-69, 2006.
[16] S. Lee, C. Lee, and H.-J. Lee, “A new multi-channel on-chip-bus architecture for system-on-chips,” in Proc. International SOC Conference, pp. 305-308, 2004.
[17] M. Ruggiero, F. Angiolini, F. Poletti, D. Bertozzi, L. Benini, and R. Zafalon, “Scalability analysis of evolving SOC interconnect protocols,” in Proc. International Symposium on System-on-Chip, pp. 169-172, 2004.
[18] C.-K. Lo and R.-S. Tsay, “Automatic generation of cycle accurate and cycle count accurate transaction level bus models from a formal model,” in Proc. Asia and South Pacific Design Automation Conference, pp. 558-563, 2009.
[19] N.Y.-C. Chang, Y.-Z. Liao, and T.-S. Chang, “Analysis of shared-link AXI,” in IET Computers and Digital Techniques, vol. 3, pp. 373-383, 2009.
[20] IBM Corporation, “Prioritization of out-of-order data transfers on shared data bus,” US Patent No. 7392353, 2008.
[21] Synopsys Ltd. Web Site, http://www.synopsys.com.