在本論文中，我們探討了低低漏電電流(IR)、低順向壓降(VF)、高崩潰電壓(VBD)、高功率蕭基二極體之設計、模擬與製造等技術之研發。文中首先提出結合可提昇崩潰電壓之低表面電場型(REduce SUrface Field, RESURF)型側超接面(Lateral Super-Junction, LSJ)結構佈局與可同時提昇崩潰特性與降低漏電電流之複晶矽護環(Guarding ring)之開發研究並進行相關製程技術之建立，同時進行元件崩潰電壓與反相漏電電流改善之數值模擬與製程製作研究。
蕭基二極體具有較傳統p/n接面二極體快速之操作特性，於電子工業如整流微波、DC-AC轉換等應用極為廣泛。隨著應用市場對高功率元件之需求，具有低IR、低VF、高VBD、高功率等特性蕭基二極體已然成為現階段研發與製作之重點。然而蕭基二極體之順向壓降與反向飽和電流主要由蕭基位障高度(b)所決定，因此較低之反向飽和電流(高的蕭基位障特性)及較低之順向壓降(低的蕭基位障特性)是背道而馳的兩個目標。於進行最小功率損耗操作考量上，蕭基二極體金-半接面之蕭基金屬之位障高須在兩者間取得妥協，同時尚須顧及高崩潰電壓與低漏電電流之要求。
本論文完成建立元件之最佳化之設計、模擬分析與製作及特性量測分析。提出一可有效進行蕭基位障高度調變、可獲致最小功率損耗蕭基二極體之模擬設計、與製程開發，其中將進一步應用於低IR、低VF與高VBD之研究成果，進行一優越特性、新穎蕭基二極體之實作與特性量測與分析。

Schottky barrier diodes (SBDs) with low forward voltage drop (VF), low reverse leakage current (IR), low power loss and high breakdown voltage (VBD), etc., have been urgently required in electronic industry. Essentially, VF and IR of SBDs are key factors in determining the power loss of SBDs for power applications, which strongly depend on the Schottky barrier height (SBH). In general, a larger SBH would result in a lower IR but a larger VF, while a lower SBH shows an inverse situation. How to solve or release the trade-off problem between VF and IR, how to improve the breakdown voltage of SBDs to approach its theoretical value, and how to minimize the power loss of SBDs without sacrificing other device properties, are still open problems in the SBDs fabrication.
In this thesis, a novel device design with a RESURF type lateral super-junction for edge termination, a novel polysilicon (poly-Si) guarding ring and related fabrication process including Boron ion implantation for IR reduction and VBD enhancement are presented to tackle the open problems mentioned above. Both theoretical and experimental studies including optimum device design and device fabrication process have been conducted in this study. Special emphasis for the theoretical study is focused on the design and simulation of edge termination with super-junction, poly-Si floating ring, guard ring, and field plate. Influence of device structural parameters used in the device geometry was investigated in detail. In this thesis, technology related to high breakdown voltage device design and fabrication process has been established.
It is found that the device and fabrication technology developed in the present study could be successfully applicable to the realization of SBDs with VBD > 110V, IR < 10uA/cm2,VF < 0.5V @1A/cm2 and an adjustable SBH (0.778~0.796 V).

[1.1] Braun, Ann. Phy. Chem. 153, 556, 1874.
[1.2] J. C. Bose, U.S. Patent 775, 840, 1904.
[1.3] W. Schottky, “Halbleitertheorie der sperrschicht,” Naturwiss. 26, 843, 1938.
[1.4] H. A. Bethe, “Theory of the Boundary of Layer of Crystal Rectifiers,” MIT Radiat Lab. Rep. 43-12, 1942.
[1.5] S. M. Sze, physics of Semiconductor Devices, 2ed. (John Wiley & Sons, New York, 1981).
[1.6] B. Jayant. Baliga, Power Semiconductor Devices, pws, Boston, 1995.
[1.7] E. H. Rhoderick, Metal-semiconductor Contacts, Clarendon. Oxford, 1978; “Transport Processed in Schottky Diodes,” in K. M. Pepper, Ed. Inst. Phys. Conf. Ser., No. 22, Institute of Physics, Manchester, England, 1974, p. 3.
[1.8] Mott, “Note on the contact between a metal and an insulator or semiconductor,” Proc. Cambr. Phil. Soc. 34, 568, 1938.
[1.9] E. H. Rhoderick, "Metal-Semiconductor Contacts" IEE Proceedings-I Solid-State and Electron Devices, 129(1), 1982, pp. 1-14
[1.10] E. H. Rhoderick and R. H. Williams, "Metal-Semiconductor Contacts", (Publishers: Clarendon Press, Oxford), 2nd Edition, 1988
[1.11] C. R. Crowell and S. M. Sze, “Current Transport in Metal-Semiconductor Structures,” Solid State Electrons, 9, 1035, 1966.
[1.12] J. M. Andrews and M. P. Lepselter, “Reverse Current-Voltage Characteristics of Metal-Silicide Schottky Diodes,” Solid State Electron., 13, 1011,1970.
[1.13] C. Y. Chang and S. M. Sze, “Carrier Transport across Metal-Semiconductor Barriers,” Solid State Electron., 13, 727, 1970.
[1.14] B. Jayant Baliga, “Trends in power semiconductor devices,” IEEE Trans. Electron Devices, vol.ED-42, no. 10, pp. 1717, 1996.
[1.15] J. L. Saltich, L. E. Clark, “Use of a Double Diffused Guard Ring to obtain near Ideal I-V Characteristics in Schottky Barrier Diodes,” Solid State Electronics, Vol. 13, pp. 857-863, 1970.
[1.16] M. P. Lepselter and S. M. Sze, Bell Systems Technology J. 47, 901, 1971.
[1.17] R. N. Gupta, W. G. Min and T. P. Chow, “A novel planarized Si trench sidewall oxide-merged p-I-n Schottky (TSOX-MPS) rectifier,” IEEE Electron Devices, vol. 20, pp. 627-629, 1999.
[1.18] Manoj Mehrotra, B. J. Baliga, Solid State Electronics, Vol. 38, no. 4, 1995.
[1.19] F. Udrea, T. Trajkovic, J. Thomson, L. Coulbeck, P. R. Waind, G. A. J. Amaratunga and P. Taylor, Proc. ISPSD’2001.
[1.20] Bor Wen Liu, Chung Len Lee, Tan Fu Lei, “ High breakdown voltage Schottky barrier diode using p+-polycrystalline silicon diffused guard ring,” Electron Letters, vol. 31, no. 22 1995.
[1-21] Bor Wen Liu and C. L. Lee, "Characteristics of high breakdown voltage Schottky barrier diodes using p+-polycrystalline-silicon diffused-guard ring,” Solid-State Electronics, vol. 44, Issue 4, pp. 631-638, Apr. 2000.
[2.1] B. J. Baliga, “High voltage device termination techniques,” Proc. Inst. Elec. Eng., pt. I, vol. 129, no. 5, Oct. 1982.
[2.2] B. Jayant. Baliga, Power Semiconductor Devices, pws, Boston, 1995.
[2.3] S. M. Sze, G. Gibbons, “Effect of junction curvature on breakdown voltage in semiconductor,” Solid State Electronics, vol. 9, pp. 831-845, 1966.
[2.4] Victor A. K. Temple, W. Tantraporn, “Junction Termination Extension of Near-Ideal Breakdown Voltage in p-n Junctions,” IEEE Trans. Electron Devices, vol. ED-33, no. 10, October, 1986.
[2.5] V. A. Temple, “Increased Avalanche Breakdown Voltage and Controlled Surface Electric fields using a Junction Termination Extension (JTE),” IEEE Trans. Electron Devices, vol. ED-30, p. 954, 1983.
[2.6] Wirojana Tantraporn, Victor A. K. Temple, “Multiple-Zone Single-Mask Junction Termination Extension-A High-Yield near-ideal breakdown voltage technology,” IEEE Trans. Electron Devices, vol. ED-34, no. 10, October, 1987.
[2.7] C. Mingues, G. Charitat, “Efficiency of Junction Termination Techniques vs Oxide Trapped Charges,” Proc. ISPSD’97.
[2.8] David C. Sheridan, Guofu Niu, J. Neil Merrett, John D. Cressler, “Comparison and Optimization of Edge Termination Techniques for SiC Power Devices,” Proc. ISPSD’01.
[2.9] T. Trajkovic, F. Udrea, P. R. Waind, G. A. J. Amaratunga, “The effect of static and dynamic parasitic charge in the termination area of high voltage devices and possible solutions,” Proc. ISPSD’2000.
[2.10] V. A. K. Temple, “ Junction termination extension (JTE), a new technique for increasing avalanche breakdown voltage and controlling surface electric field in p-n junctions,” IEDM Tech. Dig., p423, 1977.
[2.11] “Junction termination extension (JTE), a new technique for increasing avalanche breakdown voltage and controlling surface electric field in p-n junctions,” General Electric TIS Rep. 80CRD146, May 1980.
[2.12] “Increased avalanche breakdown voltage and controlled surface electric fields using a junction termination extension (JTE) technique,” IEEE Trans. Electron. Devices, vol. ED-30, p. 954, 1983.
[2.13] Dejan Krizaj, Slavko Amon, Georges Charitat, “Diffused Spiral Junction Termination Structure: Modeling and Realization,” Proc. ISPSD’97.
[2.14] Dejan Krizaj, Slavko Amon, Corinne Mingues, Georges Charitat, “Spiral Junction Termination,” IEEE Trans. Eleectron. Device, vol. 44,no. 11, Nov 1997.
[2.15] V. Macary and al. “Comparison between biased and floating guard-rings as a junction termination technique,” Proc. ISPSD Japan, pp. 230-233, 1992.
[2.16] C. Mingues, D. Kriizaj, G. Charitat, “An Efficient Junction Termination Technique: the Biased Ring Sturcture,” Proc. EPE 1997,pp 2105-2109.
[2.17] Tatsuhiko Fujihira, “ Theory of Semiconductor Superjunction Devices,” Jpn. J. Appl. Phys, vol 36, 1997.
[2.18] C. Hu: Rec. Power Electronics Specialists Conf., San Diego, 1979 (IEEE, 1979) p. 385.
[2.19] P. L. Hower, T. M. S. Heng and C. Huang: Tech. Dig. Int. Electron Device Meet., Washington D.C., 1983 (IEEE, 1983) p.87.
[2.20] H. R. Chang, F. W. Holroyd: Ext, Abstr. 175th Soc. Meet., Los Angeles, 1989 (Electrochem. Soc., 1989) 89-1, p. 86.
[2.21] S. Matsumoto, T. Ohno, H. Ishii, H. Yoshino: IEEE Trans. Electron Devices 41 (1994) 814.
[2.22] R. K. Williams, W. Grabowski, M. Darwish, H. Yilmaz, M. Chang, K. Owyang: Proc. 8th Int. Symp. Power Semiconductor Devices and IC’s, Maui, 1996, p.53.
[2.23] D. J. Coe, Europe Patent 0053854, 1982.
[2.24] X. Chen, U.S. Patent 5216275, 1993.
[2.25] J. Tihanyi, U.S. Patent 5438215, 1995.
[2.26] T. Fujihira, Japan Patent pending.
[2.27] Yuming Bai, Alex Q. Huang, Xuening Li, “Junction Termination Technique for Super Junction Devices,” Proc. ISPSD’2000.
[2.28] G. Deboy, M. Marz, J. P. Stengl, H. Strack, J. Tihanyi, H. Weber, “A new generation of high voltage MOSFETs breaks the limit line of silicon,” Proc. IEDM, 1998.
[2.29] L. Lorenz, G. Deboy, A, Knapp, M. Marz, “COOLMOSTM – a new milestone in high voltage power MOS,” Proc. ISPSD’99.
[2.30] T. Fujihira and Y. Miyasaka, “Simulated superior performances of semiconductor super junction devices,” Proc. ISPSD’98.
[2.31] Praveen M. Shenoy, Anup Bhalla, Gary M. Dolny, “ Analysis of the Effect of Charge Imbalance on the Stattic and Dynamic Characteristics of the Super Junction MOSFET,” Proc. ISPSD’99.
[2.32] M. M. De Souza, O. Spulber, E. M. Sankara Narayanan, “A Novel ‘COOL’ Insulated Base Transistor,” Proc. ISPSD’2000.
[2.33] F. Urea, T. Trajkovic, J, Thomson, L. Coulbeck, P. R. Waind, G. A. J. Amaratunga and P. Tayolr, “Ultra-high voltage device termination using the 3D RESURF (Super-Junction) concept – experimental demonstration at 6.5 kV,” Proc. ISPSD’2001.
[3.1] B. J. Baliga, “Power semiconductor device figure of merit for high-frequency applications,” IEEE Electron Device Lett., 1989.
[3.2] B. J. Baliga, “Modern Power Devices,” Wiley, New York, 1987.
[3.3] S. N. Mohammad, A. A. Salvador, H. Morkoc, “ Emerging gallium nitride based devices,” Proc. IEEE, 1995.
[3.4] Chang, C. Y., Sze S. M., “ Carrier transport metal-semiconductor barrier,” Solid State Electron., 13, 1973.
[3.5] Saltich, J. L., Clark, L. E., “ Use of a double diffused guard ring to obtain near ideal I-V characteristics in Schottky barrier diodes,” Solid State Electorn., 13, 1970.
[3.6] Bor Wen Liu, Chung Len Lee, Tan Fu Lei, “ High breakdown voltage Schottky barrier diode using p+-polycrystalline silicon diffused guard ring,” Electron Letters, vol. 31, no. 22 1995.
[3.7] R. T Tung, A. F. J. Levi, J. P. Sullivan, F. Schrey, Phys. Rev. Lett, 66, 72,1991.
[3.8] J. P. Sullivan, R. T. Tung, M. R. Pinto, W. R. Graham, J. Apply Phys. 70, 7403, 1991.
[3.9] R. T. Tung, Phys. Rev. B 45, 13509, 1992.
[3.10] Keiji Maeda, “Identity of defect causing nonideality in nearly ideal Au/n-Si Schottky barriers,” Applied Suface Science, 190, pp. 445-449, 2002.
[3.11] V. Heine, Phys. Rev. 71.717, 1947.
[3.12] S. G. Louie, J. R. Chelikowsky, M. L. Cohen, Phys. Rev. B 15, 2151, 1977.
[3.13] I. Ohdomari, K. N. Tu, “Parallel silicide contacts,” IBM T. J. Watson Research Center, Yorktown Heights, New York, 10598.
[3.14] I. Ohdomari, T. S. Kuan, K. N. Tu, J. of Appl. Phys., 50,7020, 1979.
[3.15] B. J. Baliga, power semiconductor devices.
[3.16] E. H. Rhoderick, Metal-Semiconductor Contacts, Clarendon, Oxford, 1978.
[3.17] J. P. Ponpon, P. Siffert, J. Appl. Phys. 49, 6004, 1978.
[3.18] J. A. Appels, H. M. J. Vaes, “High Voltage Thin Layer Devices (Resurf Devices),” IEDM’79, Washington, 1979.
[3.19] J. A. Appels, M. G. Collet, P. A. H. Hart, H. M. J. Vaes and J. F. C. M. Verhoeven, “Thin Layer High-Voltage Devices (RESURF Devices),” Philips J. Res. 35, 1-13, 1980.