| 研究生: |
黃以鈞 Huang, Yi-Jyung |
|---|---|
| 論文名稱: |
應用疊層多晶矽熱電偶以提升雙空腔熱電能源採集器性能之研究 Development of a High Performance Thermoelectric Energy Generator with Stacked Polysilicon Thermocouples and Double Cavity Design |
| 指導教授: |
楊世銘
Yang, S. M. |
| 學位類別: |
碩士 Master |
| 系所名稱: |
工學院 - 航空太空工程學系 Department of Aeronautics & Astronautics |
| 論文出版年: | 2021 |
| 畢業學年度: | 109 |
| 語文別: | 英文 |
| 論文頁數: | 76 |
| 中文關鍵詞: | 熱電能源採集器 、疊層設計 、CMOS 製程 、雙空腔結構 |
| 外文關鍵詞: | Thermoelectric energy generator chip, CMOS process, Stacked thermocouples, Double cavity design |
| 相關次數: | 點閱:124 下載:0 |
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熱電能源採集器可將環境中的溫差轉換為可用電能,其優點為體積小、無移動件、可靠度高、且可長時間供應穩定電源。本文提出一個高性能熱電能源採集器晶片,以多晶矽熱電偶之疊層設計增加其單位面積數量並結合雙空腔設計以增加熱電偶之溫差,藉以提升熱電能源採集器之性能。透過分析數值模型預測當熱電偶之尺寸為64 μm × 2 μm × 0.275 μm (N 型) 及 58 μm × 2 μm × 0.180 μm (P 型)時,可得熱電能源採集器元件之最佳功率係數 0.084 μW/cm2K2,電壓係數 9.136 V/cm2K。此熱電能源採集器之元件可整合於 TSMC D35 2P4M CMOS 製程以提升製程良率。此熱電能源採集器晶片之面積為 5 mm × 5 mm,分為 12 個區塊,其實驗結果顯示功率係數為 0.075 μW/cm2K2,電壓係數為 7.004 V/cm2K,此乃歷來2P4M CMOS 熱電能源採集器之最佳性能。此等性能相較於沒有疊層設計之熱電能源採集器提升了約 2.5 倍。若將此疊層設計運用於 TSMC T18 1P6M 製程,藉此製程之多晶矽有較佳的熱電能源轉換效率,則其功率係數可達 0.476 μW/cm2K2,電壓係數 60.811 V/cm2K,此功率係數約為 TSMC D35 2P4M CMOS製程之熱電能源採集器的 6 倍。成果顯示本研究開發之熱電能源採集器適用於半導體CMOS 製程,其利用薄膜製程具有高度的整合性,輕量化和可量產的優點。
Thermoelectric energy generator (TEG) can convert electrical power from temperature difference in the environment. Its advantages are small size, no moving parts, high reliability, and stable power supply. This thesis proposes a high performance TEG chip with stacked polysilicon thermocouples and double cavity design to increase the number of thermocouples in the limited area so as to improve the performance. The simulation results show the optimal thermocouple size is at 64 μm × 2 μm × 0.275 μm (N-type) and 58 μm × 2 μm × 0.180 μm (P-type), with the corresponding power factor and voltage factor is 0.084 μW/cm2K2 and 9.136 V/cm2K, respectively. The TEG chip can be integrated into the TSMC D35 2P4M CMOS process to improve process yield. For a TEG of 5 mm × 5 mm, measurement result shows that the chip can provide power factor 0.075 μW/cm2K2 and voltage factor 7.004 V/cm2K. This is the best performance of the TEG chip by D35 2P4M CMOS process about 2.5 times higher than the TEG chip without the stacked thermocouples design. If using the same design on TSMC T18 CMOS process with the polysilicon in better thermoelectric conversion, the power factor can reach 0.476 μW/cm2K2 and the voltage factor 60.811 V/cm2K, which is about 6 times of the TEG chip by TSMC D35 2P4M CMOS process. The result shows that the TEG design is suitable to the standard CMOS process for the advantages in high device integration capability, lightweight, and mass production.
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